| BaseCPU.py (8863:50ce4deacda9) | BaseCPU.py (8887:20ea02da9c53) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 200 unchanged lines hidden (view full) --- 209 self.itb_walker_cache = iwc 210 self.dtb_walker_cache = dwc 211 self.itb.walker.port = iwc.cpu_side 212 self.dtb.walker.port = dwc.cpu_side 213 self._cached_ports += ["itb_walker_cache.mem_side", \ 214 "dtb_walker_cache.mem_side"] 215 else: 216 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 200 unchanged lines hidden (view full) --- 209 self.itb_walker_cache = iwc 210 self.dtb_walker_cache = dwc 211 self.itb.walker.port = iwc.cpu_side 212 self.dtb.walker.port = dwc.cpu_side 213 self._cached_ports += ["itb_walker_cache.mem_side", \ 214 "dtb_walker_cache.mem_side"] 215 else: 216 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] |
| 217 |
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| 217 # Checker doesn't need its own tlb caches because it does 218 # functional accesses only | 218 # Checker doesn't need its own tlb caches because it does 219 # functional accesses only |
| 219 if buildEnv['USE_CHECKER']: | 220 if self.checker != NULL: |
| 220 self._cached_ports += ["checker.itb.walker.port", \ 221 "checker.dtb.walker.port"] 222 223 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 224 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 225 self.toL2Bus = Bus() 226 self.connectCachedPorts(self.toL2Bus) 227 self.l2cache = l2c 228 self.toL2Bus.master = self.l2cache.cpu_side 229 self._cached_ports = ['l2cache.mem_side'] | 221 self._cached_ports += ["checker.itb.walker.port", \ 222 "checker.dtb.walker.port"] 223 224 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 225 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 226 self.toL2Bus = Bus() 227 self.connectCachedPorts(self.toL2Bus) 228 self.l2cache = l2c 229 self.toL2Bus.master = self.l2cache.cpu_side 230 self._cached_ports = ['l2cache.mem_side'] |
| 231 232 def addCheckerCpu(self): 233 pass |
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