BaseCPU.py (8839:eeb293859255) BaseCPU.py (8863:50ce4deacda9)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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95 do_quiesce = Param.Bool(True, "enable quiesce instructions")
96
97 workload = VectorParam.Process([], "processes to run")
98
99 if buildEnv['TARGET_ISA'] == 'sparc':
100 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
101 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
102 interrupts = Param.SparcInterrupts(
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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95 do_quiesce = Param.Bool(True, "enable quiesce instructions")
96
97 workload = VectorParam.Process([], "processes to run")
98
99 if buildEnv['TARGET_ISA'] == 'sparc':
100 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
101 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
102 interrupts = Param.SparcInterrupts(
103 SparcInterrupts(), "Interrupt Controller")
103 NULL, "Interrupt Controller")
104 elif buildEnv['TARGET_ISA'] == 'alpha':
105 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
106 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
107 interrupts = Param.AlphaInterrupts(
104 elif buildEnv['TARGET_ISA'] == 'alpha':
105 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
106 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
107 interrupts = Param.AlphaInterrupts(
108 AlphaInterrupts(), "Interrupt Controller")
108 NULL, "Interrupt Controller")
109 elif buildEnv['TARGET_ISA'] == 'x86':
110 dtb = Param.X86TLB(X86TLB(), "Data TLB")
111 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
109 elif buildEnv['TARGET_ISA'] == 'x86':
110 dtb = Param.X86TLB(X86TLB(), "Data TLB")
111 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
112 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
113 interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
112 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
114 elif buildEnv['TARGET_ISA'] == 'mips':
115 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
116 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
117 interrupts = Param.MipsInterrupts(
113 elif buildEnv['TARGET_ISA'] == 'mips':
114 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
115 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
116 interrupts = Param.MipsInterrupts(
118 MipsInterrupts(), "Interrupt Controller")
117 NULL, "Interrupt Controller")
119 elif buildEnv['TARGET_ISA'] == 'arm':
120 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
121 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
122 interrupts = Param.ArmInterrupts(
118 elif buildEnv['TARGET_ISA'] == 'arm':
119 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
120 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
121 interrupts = Param.ArmInterrupts(
123 ArmInterrupts(), "Interrupt Controller")
122 NULL, "Interrupt Controller")
124 elif buildEnv['TARGET_ISA'] == 'power':
125 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
126 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
127 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
128 interrupts = Param.PowerInterrupts(
123 elif buildEnv['TARGET_ISA'] == 'power':
124 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
125 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
126 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
127 interrupts = Param.PowerInterrupts(
129 PowerInterrupts(), "Interrupt Controller")
128 NULL, "Interrupt Controller")
130 else:
131 print "Don't know what TLB to use for ISA %s" % \
132 buildEnv['TARGET_ISA']
133 sys.exit(1)
134
135 max_insts_all_threads = Param.Counter(0,
136 "terminate when all threads have reached this inst count")
137 max_insts_any_thread = Param.Counter(0,

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159 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
160
161 _uncached_slave_ports = []
162 _uncached_master_ports = []
163 if buildEnv['TARGET_ISA'] == 'x86':
164 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
165 _uncached_master_ports += ["interrupts.int_master"]
166
129 else:
130 print "Don't know what TLB to use for ISA %s" % \
131 buildEnv['TARGET_ISA']
132 sys.exit(1)
133
134 max_insts_all_threads = Param.Counter(0,
135 "terminate when all threads have reached this inst count")
136 max_insts_any_thread = Param.Counter(0,

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158 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
159
160 _uncached_slave_ports = []
161 _uncached_master_ports = []
162 if buildEnv['TARGET_ISA'] == 'x86':
163 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
164 _uncached_master_ports += ["interrupts.int_master"]
165
166 def createInterruptController(self):
167 if buildEnv['TARGET_ISA'] == 'sparc':
168 self.interrupts = SparcInterrupts()
169 elif buildEnv['TARGET_ISA'] == 'alpha':
170 self.interrupts = AlphaInterrupts()
171 elif buildEnv['TARGET_ISA'] == 'x86':
172 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
173 self.interrupts = _localApic
174 elif buildEnv['TARGET_ISA'] == 'mips':
175 self.interrupts = MipsInterrupts()
176 elif buildEnv['TARGET_ISA'] == 'arm':
177 self.interrupts = ArmInterrupts()
178 elif buildEnv['TARGET_ISA'] == 'power':
179 self.interrupts = PowerInterrupts()
180 else:
181 print "Don't know what Interrupt Controller to use for ISA %s" % \
182 buildEnv['TARGET_ISA']
183 sys.exit(1)
184
167 def connectCachedPorts(self, bus):
168 for p in self._cached_ports:
169 exec('self.%s = bus.slave' % p)
170
171 def connectUncachedPorts(self, bus):
172 for p in self._uncached_slave_ports:
173 exec('self.%s = bus.master' % p)
174 for p in self._uncached_master_ports:

--- 37 unchanged lines hidden --- 		185 def connectCachedPorts(self, bus):
186 for p in self._cached_ports:
187 exec('self.%s = bus.slave' % p)
188
189 def connectUncachedPorts(self, bus):
190 for p in self._uncached_slave_ports:
191 exec('self.%s = bus.master' % p)
192 for p in self._uncached_master_ports:

--- 37 unchanged lines hidden ---