BaseCPU.py (8809:bb10807da889) BaseCPU.py (8839:eeb293859255)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Nathan Binkert
29# Rick Strong
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;

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34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
30
31import sys
32
33from m5.defines import buildEnv
34from m5.params import *
35from m5.proxy import *
36
37from Bus import Bus

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133 defer_registration = Param.Bool(False,
134 "defer registration with system (for sampling)")
135
136 clock = Param.Clock('1t', "clock speed")
137 phase = Param.Latency('0ns', "clock phase")
138
139 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
140
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import Bus

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146 defer_registration = Param.Bool(False,
147 "defer registration with system (for sampling)")
148
149 clock = Param.Clock('1t', "clock speed")
150 phase = Param.Latency('0ns', "clock phase")
151
152 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
153
141 icache_port = Port("Instruction Port")
142 dcache_port = Port("Data Port")
154 icache_port = MasterPort("Instruction Port")
155 dcache_port = MasterPort("Data Port")
143 _cached_ports = ['icache_port', 'dcache_port']
144
145 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
146 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
147
156 _cached_ports = ['icache_port', 'dcache_port']
157
158 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
159 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
160
148 _uncached_ports = []
161 _uncached_slave_ports = []
162 _uncached_master_ports = []
149 if buildEnv['TARGET_ISA'] == 'x86':
163 if buildEnv['TARGET_ISA'] == 'x86':
150 _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
164 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
165 _uncached_master_ports += ["interrupts.int_master"]
151
152 def connectCachedPorts(self, bus):
153 for p in self._cached_ports:
166
167 def connectCachedPorts(self, bus):
168 for p in self._cached_ports:
154 exec('self.%s = bus.port' % p)
169 exec('self.%s = bus.slave' % p)
155
156 def connectUncachedPorts(self, bus):
170
171 def connectUncachedPorts(self, bus):
157 for p in self._uncached_ports:
158 exec('self.%s = bus.port' % p)
172 for p in self._uncached_slave_ports:
173 exec('self.%s = bus.master' % p)
174 for p in self._uncached_master_ports:
175 exec('self.%s = bus.slave' % p)
159
160 def connectAllPorts(self, cached_bus, uncached_bus = None):
161 self.connectCachedPorts(cached_bus)
162 if not uncached_bus:
163 uncached_bus = cached_bus
164 self.connectUncachedPorts(uncached_bus)
165
166 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):

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185 self._cached_ports += ["checker.itb.walker.port", \
186 "checker.dtb.walker.port"]
187
188 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
189 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
190 self.toL2Bus = Bus()
191 self.connectCachedPorts(self.toL2Bus)
192 self.l2cache = l2c
176
177 def connectAllPorts(self, cached_bus, uncached_bus = None):
178 self.connectCachedPorts(cached_bus)
179 if not uncached_bus:
180 uncached_bus = cached_bus
181 self.connectUncachedPorts(uncached_bus)
182
183 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):

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202 self._cached_ports += ["checker.itb.walker.port", \
203 "checker.dtb.walker.port"]
204
205 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
206 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
207 self.toL2Bus = Bus()
208 self.connectCachedPorts(self.toL2Bus)
209 self.l2cache = l2c
193 self.l2cache.cpu_side = self.toL2Bus.port
210 self.toL2Bus.master = self.l2cache.cpu_side
194 self._cached_ports = ['l2cache.mem_side']
211 self._cached_ports = ['l2cache.mem_side']