BaseCPU.py (8796:a2ae5c378d0a) BaseCPU.py (8799:dac1e33e07b0)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 124 unchanged lines hidden (view full) ---

133 defer_registration = Param.Bool(False,
134 "defer registration with system (for sampling)")
135
136 clock = Param.Clock('1t', "clock speed")
137 phase = Param.Latency('0ns', "clock phase")
138
139 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
140
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 124 unchanged lines hidden (view full) ---

133 defer_registration = Param.Bool(False,
134 "defer registration with system (for sampling)")
135
136 clock = Param.Clock('1t', "clock speed")
137 phase = Param.Latency('0ns', "clock phase")
138
139 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
140
141 _cached_ports = []
141 icache_port = Port("Instruction Port")
142 dcache_port = Port("Data Port")
143 _cached_ports = ['icache_port', 'dcache_port']
144
142 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
145 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
143 _cached_ports = ["itb.walker.port", "dtb.walker.port"]
146 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
144
145 _uncached_ports = []
146 if buildEnv['TARGET_ISA'] == 'x86':
147 _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
148
149 def connectCachedPorts(self, bus):
150 for p in self._cached_ports:
151 exec('self.%s = bus.port' % p)

--- 36 unchanged lines hidden --- 		147
148 _uncached_ports = []
149 if buildEnv['TARGET_ISA'] == 'x86':
150 _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
151
152 def connectCachedPorts(self, bus):
153 for p in self._cached_ports:
154 exec('self.%s = bus.port' % p)

--- 36 unchanged lines hidden ---