BaseCPU.py (8793:5f25086326ac) BaseCPU.py (8796:a2ae5c378d0a)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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162
163 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
164 assert(len(self._cached_ports) < 7)
165 self.icache = ic
166 self.dcache = dc
167 self.icache_port = ic.cpu_side
168 self.dcache_port = dc.cpu_side
169 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 153 unchanged lines hidden (view full) ---

162
163 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
164 assert(len(self._cached_ports) < 7)
165 self.icache = ic
166 self.dcache = dc
167 self.icache_port = ic.cpu_side
168 self.dcache_port = dc.cpu_side
169 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
170 if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc:
171 self.itb_walker_cache = iwc
172 self.dtb_walker_cache = dwc
173 self.itb.walker.port = iwc.cpu_side
174 self.dtb.walker.port = dwc.cpu_side
175 self._cached_ports += ["itb_walker_cache.mem_side", \
176 "dtb_walker_cache.mem_side"]
177 elif buildEnv['TARGET_ISA'] == 'arm':
178 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
170 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
171 if iwc and dwc:
172 self.itb_walker_cache = iwc
173 self.dtb_walker_cache = dwc
174 self.itb.walker.port = iwc.cpu_side
175 self.dtb.walker.port = dwc.cpu_side
176 self._cached_ports += ["itb_walker_cache.mem_side", \
177 "dtb_walker_cache.mem_side"]
178 else:
179 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
179
180 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
181 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
182 self.toL2Bus = Bus()
183 self.connectCachedPorts(self.toL2Bus)
184 self.l2cache = l2c
185 self.l2cache.cpu_side = self.toL2Bus.port
186 self._cached_ports = ['l2cache.mem_side']
180
181 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
182 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
183 self.toL2Bus = Bus()
184 self.connectCachedPorts(self.toL2Bus)
185 self.l2cache = l2c
186 self.l2cache.cpu_side = self.toL2Bus.port
187 self._cached_ports = ['l2cache.mem_side']