BaseCPU.py (8752:28e899b7dee3) | BaseCPU.py (8756:cce8cf3906ca) |
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1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 126 unchanged lines hidden (view full) --- 135 "defer registration with system (for sampling)") 136 137 clock = Param.Clock('1t', "clock speed") 138 phase = Param.Latency('0ns', "clock phase") 139 140 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 141 142 _cached_ports = [] | 1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 126 unchanged lines hidden (view full) --- 135 "defer registration with system (for sampling)") 136 137 clock = Param.Clock('1t', "clock speed") 138 phase = Param.Latency('0ns', "clock phase") 139 140 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 141 142 _cached_ports = [] |
143 if buildEnv['TARGET_ISA'] == 'x86' or \ 144 (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']): | 143 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: |
145 _cached_ports = ["itb.walker.port", "dtb.walker.port"] 146 147 _uncached_ports = [] 148 if buildEnv['TARGET_ISA'] == 'x86': 149 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 150 151 def connectCachedPorts(self, bus): 152 for p in self._cached_ports: --- 11 unchanged lines hidden (view full) --- 164 165 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 166 assert(len(self._cached_ports) < 7) 167 self.icache = ic 168 self.dcache = dc 169 self.icache_port = ic.cpu_side 170 self.dcache_port = dc.cpu_side 171 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] | 144 _cached_ports = ["itb.walker.port", "dtb.walker.port"] 145 146 _uncached_ports = [] 147 if buildEnv['TARGET_ISA'] == 'x86': 148 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 149 150 def connectCachedPorts(self, bus): 151 for p in self._cached_ports: --- 11 unchanged lines hidden (view full) --- 163 164 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 165 assert(len(self._cached_ports) < 7) 166 self.icache = ic 167 self.dcache = dc 168 self.icache_port = ic.cpu_side 169 self.dcache_port = dc.cpu_side 170 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] |
172 if buildEnv['FULL_SYSTEM']: 173 if buildEnv['TARGET_ISA'] == 'x86': 174 self.itb_walker_cache = iwc 175 self.dtb_walker_cache = dwc 176 self.itb.walker.port = iwc.cpu_side 177 self.dtb.walker.port = dwc.cpu_side 178 self._cached_ports += ["itb_walker_cache.mem_side", \ 179 "dtb_walker_cache.mem_side"] 180 elif buildEnv['TARGET_ISA'] == 'arm': 181 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] | 171 if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc: 172 self.itb_walker_cache = iwc 173 self.dtb_walker_cache = dwc 174 self.itb.walker.port = iwc.cpu_side 175 self.dtb.walker.port = dwc.cpu_side 176 self._cached_ports += ["itb_walker_cache.mem_side", \ 177 "dtb_walker_cache.mem_side"] 178 elif buildEnv['TARGET_ISA'] == 'arm': 179 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] |
182 183 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 184 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 185 self.toL2Bus = Bus() 186 self.connectCachedPorts(self.toL2Bus) 187 self.l2cache = l2c 188 self.l2cache.cpu_side = self.toL2Bus.port 189 self._cached_ports = ['l2cache.mem_side'] | 180 181 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 182 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 183 self.toL2Bus = Bus() 184 self.connectCachedPorts(self.toL2Bus) 185 self.l2cache = l2c 186 self.l2cache.cpu_side = self.toL2Bus.port 187 self._cached_ports = ['l2cache.mem_side'] |