BaseCPU.py (8733:64a7bf8fa56c) | BaseCPU.py (8745:575cab0db076) |
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1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38from InstTracer import InstTracer 39from ExeTracer import ExeTracer 40from MemObject import MemObject 41 42default_tracer = ExeTracer() 43 44if buildEnv['TARGET_ISA'] == 'alpha': 45 from AlphaTLB import AlphaDTB, AlphaITB | 1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38from InstTracer import InstTracer 39from ExeTracer import ExeTracer 40from MemObject import MemObject 41 42default_tracer = ExeTracer() 43 44if buildEnv['TARGET_ISA'] == 'alpha': 45 from AlphaTLB import AlphaDTB, AlphaITB |
46 if buildEnv['FULL_SYSTEM']: 47 from AlphaInterrupts import AlphaInterrupts | 46 from AlphaInterrupts import AlphaInterrupts |
48elif buildEnv['TARGET_ISA'] == 'sparc': 49 from SparcTLB import SparcTLB | 47elif buildEnv['TARGET_ISA'] == 'sparc': 48 from SparcTLB import SparcTLB |
50 if buildEnv['FULL_SYSTEM']: 51 from SparcInterrupts import SparcInterrupts | 49 from SparcInterrupts import SparcInterrupts |
52elif buildEnv['TARGET_ISA'] == 'x86': 53 from X86TLB import X86TLB | 50elif buildEnv['TARGET_ISA'] == 'x86': 51 from X86TLB import X86TLB |
54 if buildEnv['FULL_SYSTEM']: 55 from X86LocalApic import X86LocalApic | 52 from X86LocalApic import X86LocalApic |
56elif buildEnv['TARGET_ISA'] == 'mips': 57 from MipsTLB import MipsTLB | 53elif buildEnv['TARGET_ISA'] == 'mips': 54 from MipsTLB import MipsTLB |
58 if buildEnv['FULL_SYSTEM']: 59 from MipsInterrupts import MipsInterrupts | 55 from MipsInterrupts import MipsInterrupts |
60elif buildEnv['TARGET_ISA'] == 'arm': 61 from ArmTLB import ArmTLB | 56elif buildEnv['TARGET_ISA'] == 'arm': 57 from ArmTLB import ArmTLB |
62 if buildEnv['FULL_SYSTEM']: 63 from ArmInterrupts import ArmInterrupts | 58 from ArmInterrupts import ArmInterrupts |
64elif buildEnv['TARGET_ISA'] == 'power': 65 from PowerTLB import PowerTLB | 59elif buildEnv['TARGET_ISA'] == 'power': 60 from PowerTLB import PowerTLB |
66 if buildEnv['FULL_SYSTEM']: 67 from PowerInterrupts import PowerInterrupts | 61 from PowerInterrupts import PowerInterrupts |
68 69class BaseCPU(MemObject): 70 type = 'BaseCPU' 71 abstract = True 72 73 system = Param.System(Parent.any, "system object") 74 cpu_id = Param.Int(-1, "CPU identifier") 75 numThreads = Param.Unsigned(1, "number of HW thread contexts") --- 12 unchanged lines hidden (view full) --- 88 profile = Param.Latency('0ns', "trace the kernel stack") 89 do_quiesce = Param.Bool(True, "enable quiesce instructions") 90 else: 91 workload = VectorParam.Process("processes to run") 92 93 if buildEnv['TARGET_ISA'] == 'sparc': 94 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 95 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") | 62 63class BaseCPU(MemObject): 64 type = 'BaseCPU' 65 abstract = True 66 67 system = Param.System(Parent.any, "system object") 68 cpu_id = Param.Int(-1, "CPU identifier") 69 numThreads = Param.Unsigned(1, "number of HW thread contexts") --- 12 unchanged lines hidden (view full) --- 82 profile = Param.Latency('0ns', "trace the kernel stack") 83 do_quiesce = Param.Bool(True, "enable quiesce instructions") 84 else: 85 workload = VectorParam.Process("processes to run") 86 87 if buildEnv['TARGET_ISA'] == 'sparc': 88 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 89 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") |
96 if buildEnv['FULL_SYSTEM']: 97 interrupts = Param.SparcInterrupts( | 90 interrupts = Param.SparcInterrupts( |
98 SparcInterrupts(), "Interrupt Controller") 99 elif buildEnv['TARGET_ISA'] == 'alpha': 100 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 101 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") | 91 SparcInterrupts(), "Interrupt Controller") 92 elif buildEnv['TARGET_ISA'] == 'alpha': 93 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 94 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") |
102 if buildEnv['FULL_SYSTEM']: 103 interrupts = Param.AlphaInterrupts( | 95 interrupts = Param.AlphaInterrupts( |
104 AlphaInterrupts(), "Interrupt Controller") 105 elif buildEnv['TARGET_ISA'] == 'x86': 106 dtb = Param.X86TLB(X86TLB(), "Data TLB") 107 itb = Param.X86TLB(X86TLB(), "Instruction TLB") | 96 AlphaInterrupts(), "Interrupt Controller") 97 elif buildEnv['TARGET_ISA'] == 'x86': 98 dtb = Param.X86TLB(X86TLB(), "Data TLB") 99 itb = Param.X86TLB(X86TLB(), "Instruction TLB") |
108 if buildEnv['FULL_SYSTEM']: 109 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 110 interrupts = \ 111 Param.X86LocalApic(_localApic, "Interrupt Controller") | 100 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 101 interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") |
112 elif buildEnv['TARGET_ISA'] == 'mips': 113 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 114 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") | 102 elif buildEnv['TARGET_ISA'] == 'mips': 103 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 104 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") |
115 if buildEnv['FULL_SYSTEM']: 116 interrupts = Param.MipsInterrupts( 117 MipsInterrupts(), "Interrupt Controller") | 105 interrupts = Param.MipsInterrupts( 106 MipsInterrupts(), "Interrupt Controller") |
118 elif buildEnv['TARGET_ISA'] == 'arm': 119 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 120 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") | 107 elif buildEnv['TARGET_ISA'] == 'arm': 108 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 109 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") |
121 if buildEnv['FULL_SYSTEM']: 122 interrupts = Param.ArmInterrupts( 123 ArmInterrupts(), "Interrupt Controller") | 110 interrupts = Param.ArmInterrupts( 111 ArmInterrupts(), "Interrupt Controller") |
124 elif buildEnv['TARGET_ISA'] == 'power': 125 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 126 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 127 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") | 112 elif buildEnv['TARGET_ISA'] == 'power': 113 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 114 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 115 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") |
128 if buildEnv['FULL_SYSTEM']: 129 interrupts = Param.PowerInterrupts( 130 PowerInterrupts(), "Interrupt Controller") | 116 interrupts = Param.PowerInterrupts( 117 PowerInterrupts(), "Interrupt Controller") |
131 else: 132 print "Don't know what TLB to use for ISA %s" % \ 133 buildEnv['TARGET_ISA'] 134 sys.exit(1) 135 136 max_insts_all_threads = Param.Counter(0, 137 "terminate when all threads have reached this inst count") 138 max_insts_any_thread = Param.Counter(0, --- 8 unchanged lines hidden (view full) --- 147 defer_registration = Param.Bool(False, 148 "defer registration with system (for sampling)") 149 150 clock = Param.Clock('1t', "clock speed") 151 phase = Param.Latency('0ns', "clock phase") 152 153 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 154 | 118 else: 119 print "Don't know what TLB to use for ISA %s" % \ 120 buildEnv['TARGET_ISA'] 121 sys.exit(1) 122 123 max_insts_all_threads = Param.Counter(0, 124 "terminate when all threads have reached this inst count") 125 max_insts_any_thread = Param.Counter(0, --- 8 unchanged lines hidden (view full) --- 134 defer_registration = Param.Bool(False, 135 "defer registration with system (for sampling)") 136 137 clock = Param.Clock('1t', "clock speed") 138 phase = Param.Latency('0ns', "clock phase") 139 140 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 141 |
155 icache_port = Port("Instruction Port") 156 dcache_port = Port("Data Port") 157 _cached_ports = ['icache_port', 'dcache_port'] 158 | 142 _cached_ports = [] |
159 if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: | 143 if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: |
160 _cached_ports += ["itb.walker.port", "dtb.walker.port"] | 144 _cached_ports = ["itb.walker.port", "dtb.walker.port"] |
161 162 _uncached_ports = [] | 145 146 _uncached_ports = [] |
163 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: | 147 if buildEnv['TARGET_ISA'] == 'x86': |
164 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 165 166 def connectCachedPorts(self, bus): 167 for p in self._cached_ports: 168 exec('self.%s = bus.port' % p) 169 170 def connectUncachedPorts(self, bus): 171 for p in self._uncached_ports: 172 exec('self.%s = bus.port' % p) 173 174 def connectAllPorts(self, cached_bus, uncached_bus = None): 175 self.connectCachedPorts(cached_bus) 176 if not uncached_bus: 177 uncached_bus = cached_bus 178 self.connectUncachedPorts(uncached_bus) 179 180 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): | 148 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 149 150 def connectCachedPorts(self, bus): 151 for p in self._cached_ports: 152 exec('self.%s = bus.port' % p) 153 154 def connectUncachedPorts(self, bus): 155 for p in self._uncached_ports: 156 exec('self.%s = bus.port' % p) 157 158 def connectAllPorts(self, cached_bus, uncached_bus = None): 159 self.connectCachedPorts(cached_bus) 160 if not uncached_bus: 161 uncached_bus = cached_bus 162 self.connectUncachedPorts(uncached_bus) 163 164 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): |
165 assert(len(self._cached_ports) < 7) |
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181 self.icache = ic 182 self.dcache = dc 183 self.icache_port = ic.cpu_side 184 self.dcache_port = dc.cpu_side 185 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 186 if buildEnv['FULL_SYSTEM']: | 166 self.icache = ic 167 self.dcache = dc 168 self.icache_port = ic.cpu_side 169 self.dcache_port = dc.cpu_side 170 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 171 if buildEnv['FULL_SYSTEM']: |
187 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 188 if iwc and dwc: 189 self.itb_walker_cache = iwc 190 self.dtb_walker_cache = dwc 191 self.itb.walker.port = iwc.cpu_side 192 self.dtb.walker.port = dwc.cpu_side 193 self._cached_ports += ["itb_walker_cache.mem_side", \ 194 "dtb_walker_cache.mem_side"] 195 else: 196 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 197 # Checker doesn't need its own tlb caches because it does 198 # functional accesses only 199 if buildEnv['USE_CHECKER']: 200 self._cached_ports += ["checker.itb.walker.port", \ 201 "checker.dtb.walker.port"] | 172 if buildEnv['TARGET_ISA'] == 'x86': 173 self.itb_walker_cache = iwc 174 self.dtb_walker_cache = dwc 175 self.itb.walker.port = iwc.cpu_side 176 self.dtb.walker.port = dwc.cpu_side 177 self._cached_ports += ["itb_walker_cache.mem_side", \ 178 "dtb_walker_cache.mem_side"] 179 elif buildEnv['TARGET_ISA'] == 'arm': 180 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] |
202 203 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 204 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 205 self.toL2Bus = Bus() 206 self.connectCachedPorts(self.toL2Bus) 207 self.l2cache = l2c 208 self.l2cache.cpu_side = self.toL2Bus.port 209 self._cached_ports = ['l2cache.mem_side'] | 181 182 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 183 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 184 self.toL2Bus = Bus() 185 self.connectCachedPorts(self.toL2Bus) 186 self.l2cache = l2c 187 self.l2cache.cpu_side = self.toL2Bus.port 188 self._cached_ports = ['l2cache.mem_side'] |