BaseCPU.py (8707:489489c67fd9) | BaseCPU.py (8733:64a7bf8fa56c) |
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1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 164 unchanged lines hidden (view full) --- 173 174 def connectAllPorts(self, cached_bus, uncached_bus = None): 175 self.connectCachedPorts(cached_bus) 176 if not uncached_bus: 177 uncached_bus = cached_bus 178 self.connectUncachedPorts(uncached_bus) 179 180 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): | 1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 164 unchanged lines hidden (view full) --- 173 174 def connectAllPorts(self, cached_bus, uncached_bus = None): 175 self.connectCachedPorts(cached_bus) 176 if not uncached_bus: 177 uncached_bus = cached_bus 178 self.connectUncachedPorts(uncached_bus) 179 180 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): |
181 assert(len(self._cached_ports) < 7) | |
182 self.icache = ic 183 self.dcache = dc 184 self.icache_port = ic.cpu_side 185 self.dcache_port = dc.cpu_side 186 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 187 if buildEnv['FULL_SYSTEM']: 188 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 189 if iwc and dwc: 190 self.itb_walker_cache = iwc 191 self.dtb_walker_cache = dwc 192 self.itb.walker.port = iwc.cpu_side 193 self.dtb.walker.port = dwc.cpu_side 194 self._cached_ports += ["itb_walker_cache.mem_side", \ 195 "dtb_walker_cache.mem_side"] 196 else: 197 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] | 181 self.icache = ic 182 self.dcache = dc 183 self.icache_port = ic.cpu_side 184 self.dcache_port = dc.cpu_side 185 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 186 if buildEnv['FULL_SYSTEM']: 187 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 188 if iwc and dwc: 189 self.itb_walker_cache = iwc 190 self.dtb_walker_cache = dwc 191 self.itb.walker.port = iwc.cpu_side 192 self.dtb.walker.port = dwc.cpu_side 193 self._cached_ports += ["itb_walker_cache.mem_side", \ 194 "dtb_walker_cache.mem_side"] 195 else: 196 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] |
197 # Checker doesn't need its own tlb caches because it does 198 # functional accesses only 199 if buildEnv['USE_CHECKER']: 200 self._cached_ports += ["checker.itb.walker.port", \ 201 "checker.dtb.walker.port"] |
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198 199 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 200 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 201 self.toL2Bus = Bus() 202 self.connectCachedPorts(self.toL2Bus) 203 self.l2cache = l2c 204 self.l2cache.cpu_side = self.toL2Bus.port 205 self._cached_ports = ['l2cache.mem_side'] | 202 203 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 204 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 205 self.toL2Bus = Bus() 206 self.connectCachedPorts(self.toL2Bus) 207 self.l2cache = l2c 208 self.l2cache.cpu_side = self.toL2Bus.port 209 self._cached_ports = ['l2cache.mem_side'] |