Cross Reference: /gem5/src/cpu/BaseCPU.py

Deleted Added

sdiff udiff text old ( 7897:d9e8b1fd1a9f ) new ( 8181:f789b9aac5f4 )

full compact

BaseCPU.py (7897:d9e8b1fd1a9f)	BaseCPU.py (8181:f789b9aac5f4)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 185 unchanged lines hidden (view full) --- 194 195 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 196 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 197 self.toL2Bus = Bus() 198 self.connectCachedPorts(self.toL2Bus) 199 self.l2cache = l2c 200 self.l2cache.cpu_side = self.toL2Bus.port 201 self._cached_ports = ['l2cache.mem_side']	1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 185 unchanged lines hidden (view full) --- 194 195 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 196 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 197 self.toL2Bus = Bus() 198 self.connectCachedPorts(self.toL2Bus) 199 self.l2cache = l2c 200 self.l2cache.cpu_side = self.toL2Bus.port 201 self._cached_ports = ['l2cache.mem_side']
202 203 if buildEnv['TARGET_ISA'] == 'mips': 204 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 205 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 206 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 207 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 208 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 209 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 210 CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 211 CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") 212 CP0_Config_BE = Param.Unsigned(0,"Big Endian?") 213 CP0_Config_AT = Param.Unsigned(0,"No Description") 214 CP0_Config_AR = Param.Unsigned(0,"No Description") 215 CP0_Config_MT = Param.Unsigned(0,"No Description") 216 CP0_Config_VI = Param.Unsigned(0,"No Description") 217 CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") 218 CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") 219 CP0_Config1_IS = Param.Unsigned(0,"No Description") 220 CP0_Config1_IL = Param.Unsigned(0,"No Description") 221 CP0_Config1_IA = Param.Unsigned(0,"No Description") 222 CP0_Config1_DS = Param.Unsigned(0,"No Description") 223 CP0_Config1_DL = Param.Unsigned(0,"No Description") 224 CP0_Config1_DA = Param.Unsigned(0,"No Description") 225 CP0_Config1_C2 = Param.Bool(False,"No Description") 226 CP0_Config1_MD = Param.Bool(False,"No Description") 227 CP0_Config1_PC = Param.Bool(False,"No Description") 228 CP0_Config1_WR = Param.Bool(False,"No Description") 229 CP0_Config1_CA = Param.Bool(False,"No Description") 230 CP0_Config1_EP = Param.Bool(False,"No Description") 231 CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") 232 CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") 233 CP0_Config2_TU = Param.Unsigned(0,"No Description") 234 CP0_Config2_TS = Param.Unsigned(0,"No Description") 235 CP0_Config2_TL = Param.Unsigned(0,"No Description") 236 CP0_Config2_TA = Param.Unsigned(0,"No Description") 237 CP0_Config2_SU = Param.Unsigned(0,"No Description") 238 CP0_Config2_SS = Param.Unsigned(0,"No Description") 239 CP0_Config2_SL = Param.Unsigned(0,"No Description") 240 CP0_Config2_SA = Param.Unsigned(0,"No Description") 241 CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") 242 CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") 243 CP0_Config3_LPA = Param.Bool(False,"No Description") 244 CP0_Config3_VEIC = Param.Bool(False,"No Description") 245 CP0_Config3_VInt = Param.Bool(False,"No Description") 246 CP0_Config3_SP = Param.Bool(False,"No Description") 247 CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") 248 CP0_Config3_SM = Param.Bool(False,"No Description") 249 CP0_Config3_TL = Param.Bool(False,"No Description") 250 CP0_WatchHi_M = Param.Bool(False,"No Description") 251 CP0_PerfCtr_M = Param.Bool(False,"No Description") 252 CP0_PerfCtr_W = Param.Bool(False,"No Description") 253 CP0_PRId = Param.Unsigned(0,"CP0 Status Register") 254 CP0_Config = Param.Unsigned(0,"CP0 Config Register") 255 CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") 256 CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") 257 CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")