BaseCPU.py (7868:6029008db669) BaseCPU.py (7876:189b9b258779)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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145 defer_registration = Param.Bool(False,
146 "defer registration with system (for sampling)")
147
148 clock = Param.Clock('1t', "clock speed")
149 phase = Param.Latency('0ns', "clock phase")
150
151 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
152
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 136 unchanged lines hidden (view full) ---

145 defer_registration = Param.Bool(False,
146 "defer registration with system (for sampling)")
147
148 clock = Param.Clock('1t', "clock speed")
149 phase = Param.Latency('0ns', "clock phase")
150
151 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
152
153 _mem_ports = []
153 _cached_ports = []
154 if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
155 _cached_ports = ["itb.walker.port", "dtb.walker.port"]
156
157 _uncached_ports = []
154 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
158 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
155 _mem_ports = ["itb.walker.port",
156 "dtb.walker.port",
157 "interrupts.pio",
158 "interrupts.int_port"]
159 _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
159
160
160 if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']:
161 _mem_ports = ["itb.walker.port",
162 "dtb.walker.port"]
161 def connectCachedPorts(self, bus):
162 for p in self._cached_ports:
163 exec('self.%s = bus.port' % p)
163
164
164 def connectMemPorts(self, bus):
165 for p in self._mem_ports:
166 if p != 'physmem_port':
167 exec('self.%s = bus.port' % p)
165 def connectUncachedPorts(self, bus):
166 for p in self._uncached_ports:
167 exec('self.%s = bus.port' % p)
168
168
169 def connectAllPorts(self, cached_bus, uncached_bus = None):
170 self.connectCachedPorts(cached_bus)
171 if not uncached_bus:
172 uncached_bus = cached_bus
173 self.connectUncachedPorts(uncached_bus)
174
169 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
175 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
170 assert(len(self._mem_ports) < 8)
176 assert(len(self._cached_ports) < 7)
171 self.icache = ic
172 self.dcache = dc
173 self.icache_port = ic.cpu_side
174 self.dcache_port = dc.cpu_side
177 self.icache = ic
178 self.dcache = dc
179 self.icache_port = ic.cpu_side
180 self.dcache_port = dc.cpu_side
175 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
181 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
176 if buildEnv['FULL_SYSTEM']:
177 if buildEnv['TARGET_ISA'] == 'x86':
178 self.itb_walker_cache = iwc
179 self.dtb_walker_cache = dwc
180 self.itb.walker.port = iwc.cpu_side
181 self.dtb.walker.port = dwc.cpu_side
182 if buildEnv['FULL_SYSTEM']:
183 if buildEnv['TARGET_ISA'] == 'x86':
184 self.itb_walker_cache = iwc
185 self.dtb_walker_cache = dwc
186 self.itb.walker.port = iwc.cpu_side
187 self.dtb.walker.port = dwc.cpu_side
182 self._mem_ports += ["itb_walker_cache.mem_side", \
183 "dtb_walker_cache.mem_side"]
184 self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
188 self._cached_ports += ["itb_walker_cache.mem_side", \
189 "dtb_walker_cache.mem_side"]
185 elif buildEnv['TARGET_ISA'] == 'arm':
190 elif buildEnv['TARGET_ISA'] == 'arm':
186 self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
191 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
187
188 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
189 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
190 self.toL2Bus = Bus()
192
193 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
194 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
195 self.toL2Bus = Bus()
191 self.connectMemPorts(self.toL2Bus)
196 self.connectCachedPorts(self.toL2Bus)
192 self.l2cache = l2c
193 self.l2cache.cpu_side = self.toL2Bus.port
197 self.l2cache = l2c
198 self.l2cache.cpu_side = self.toL2Bus.port
194 self._mem_ports = ['l2cache.mem_side']
199 self._cached_ports = ['l2cache.mem_side']
195
196 if buildEnv['TARGET_ISA'] == 'mips':
197 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
198 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
199 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
200 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
201 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
202 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")

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201 if buildEnv['TARGET_ISA'] == 'mips':
202 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
203 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
204 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
205 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
206 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
207 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")

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