BaseCPU.py (7404:bfc74724914e) BaseCPU.py (7776:865e37d507c7)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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162 "dtb.walker.port"]
163
164 def connectMemPorts(self, bus):
165 for p in self._mem_ports:
166 if p != 'physmem_port':
167 exec('self.%s = bus.port' % p)
168
169 def addPrivateSplitL1Caches(self, ic, dc):
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 153 unchanged lines hidden (view full) ---

162 "dtb.walker.port"]
163
164 def connectMemPorts(self, bus):
165 for p in self._mem_ports:
166 if p != 'physmem_port':
167 exec('self.%s = bus.port' % p)
168
169 def addPrivateSplitL1Caches(self, ic, dc):
170 assert(len(self._mem_ports) < 6)
170 assert(len(self._mem_ports) < 8)
171 self.icache = ic
172 self.dcache = dc
173 self.icache_port = ic.cpu_side
174 self.dcache_port = dc.cpu_side
175 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
176 if buildEnv['FULL_SYSTEM']:
177 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
178 self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
171 self.icache = ic
172 self.dcache = dc
173 self.icache_port = ic.cpu_side
174 self.dcache_port = dc.cpu_side
175 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
176 if buildEnv['FULL_SYSTEM']:
177 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
178 self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
179 if buildEnv['TARGET_ISA'] == 'x86':
180 self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
179
180 def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
181 self.addPrivateSplitL1Caches(ic, dc)
182 self.toL2Bus = Bus()
183 self.connectMemPorts(self.toL2Bus)
184 self.l2cache = l2c
185 self.l2cache.cpu_side = self.toL2Bus.port
186 self._mem_ports = ['l2cache.mem_side']

--- 56 unchanged lines hidden --- 		181
182 def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
183 self.addPrivateSplitL1Caches(ic, dc)
184 self.toL2Bus = Bus()
185 self.connectMemPorts(self.toL2Bus)
186 self.l2cache = l2c
187 self.l2cache.cpu_side = self.toL2Bus.port
188 self._mem_ports = ['l2cache.mem_side']

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