BaseCPU.py (6654:4c84e771cca7) BaseCPU.py (6691:cd68b6ecd68d)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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54elif buildEnv['TARGET_ISA'] == 'mips':
55 from MipsTLB import MipsTLB
56 if buildEnv['FULL_SYSTEM']:
57 from MipsInterrupts import MipsInterrupts
58elif buildEnv['TARGET_ISA'] == 'arm':
59 from ArmTLB import ArmTLB
60 if buildEnv['FULL_SYSTEM']:
61 from ArmInterrupts import ArmInterrupts
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 45 unchanged lines hidden (view full) ---

54elif buildEnv['TARGET_ISA'] == 'mips':
55 from MipsTLB import MipsTLB
56 if buildEnv['FULL_SYSTEM']:
57 from MipsInterrupts import MipsInterrupts
58elif buildEnv['TARGET_ISA'] == 'arm':
59 from ArmTLB import ArmTLB
60 if buildEnv['FULL_SYSTEM']:
61 from ArmInterrupts import ArmInterrupts
62elif buildEnv['TARGET_ISA'] == 'power':
63 from PowerTLB import PowerTLB
64 if buildEnv['FULL_SYSTEM']:
65 from PowerInterrupts import PowerInterrupts
62
63class BaseCPU(MemObject):
64 type = 'BaseCPU'
65 abstract = True
66
67 system = Param.System(Parent.any, "system object")
68 cpu_id = Param.Int(-1, "CPU identifier")
69 numThreads = Param.Unsigned(1, "number of HW thread contexts")

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111 MipsInterrupts(), "Interrupt Controller")
112 elif buildEnv['TARGET_ISA'] == 'arm':
113 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
114 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
115 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
116 if buildEnv['FULL_SYSTEM']:
117 interrupts = Param.ArmInterrupts(
118 ArmInterrupts(), "Interrupt Controller")
66
67class BaseCPU(MemObject):
68 type = 'BaseCPU'
69 abstract = True
70
71 system = Param.System(Parent.any, "system object")
72 cpu_id = Param.Int(-1, "CPU identifier")
73 numThreads = Param.Unsigned(1, "number of HW thread contexts")

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115 MipsInterrupts(), "Interrupt Controller")
116 elif buildEnv['TARGET_ISA'] == 'arm':
117 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
118 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
119 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
120 if buildEnv['FULL_SYSTEM']:
121 interrupts = Param.ArmInterrupts(
122 ArmInterrupts(), "Interrupt Controller")
123 elif buildEnv['TARGET_ISA'] == 'power':
124 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
125 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
126 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
127 if buildEnv['FULL_SYSTEM']:
128 interrupts = Param.PowerInterrupts(
129 PowerInterrupts(), "Interrupt Controller")
119 else:
120 print "Don't know what TLB to use for ISA %s" % \
121 buildEnv['TARGET_ISA']
122 sys.exit(1)
123
124 max_insts_all_threads = Param.Counter(0,
125 "terminate when all threads have reached this inst count")
126 max_insts_any_thread = Param.Counter(0,

--- 101 unchanged lines hidden --- 		130 else:
131 print "Don't know what TLB to use for ISA %s" % \
132 buildEnv['TARGET_ISA']
133 sys.exit(1)
134
135 max_insts_all_threads = Param.Counter(0,
136 "terminate when all threads have reached this inst count")
137 max_insts_any_thread = Param.Counter(0,

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