BaseCPU.py (6023:47b4fcb10c11) BaseCPU.py (6116:a5a97b04d796)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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49 from X86TLB import X86TLB
50 if build_env['FULL_SYSTEM']:
51 from X86LocalApic import X86LocalApic
52elif build_env['TARGET_ISA'] == 'mips':
53 from MipsTLB import MipsTLB
54 if build_env['FULL_SYSTEM']:
55 from MipsInterrupts import MipsInterrupts
56elif build_env['TARGET_ISA'] == 'arm':
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 40 unchanged lines hidden (view full) ---

49 from X86TLB import X86TLB
50 if build_env['FULL_SYSTEM']:
51 from X86LocalApic import X86LocalApic
52elif build_env['TARGET_ISA'] == 'mips':
53 from MipsTLB import MipsTLB
54 if build_env['FULL_SYSTEM']:
55 from MipsInterrupts import MipsInterrupts
56elif build_env['TARGET_ISA'] == 'arm':
57 from ArmTLB import ArmDTB
57 from ArmTLB import ArmTLB
58 if build_env['FULL_SYSTEM']:
59 from ArmInterrupts import ArmInterrupts
60
61class BaseCPU(MemObject):
62 type = 'BaseCPU'
63 abstract = True
64
65 system = Param.System(Parent.any, "system object")

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104 elif build_env['TARGET_ISA'] == 'mips':
105 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
106 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
107 if build_env['FULL_SYSTEM']:
108 interrupts = Param.MipsInterrupts(
109 MipsInterrupts(), "Interrupt Controller")
110 elif build_env['TARGET_ISA'] == 'arm':
111 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
58 if build_env['FULL_SYSTEM']:
59 from ArmInterrupts import ArmInterrupts
60
61class BaseCPU(MemObject):
62 type = 'BaseCPU'
63 abstract = True
64
65 system = Param.System(Parent.any, "system object")

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104 elif build_env['TARGET_ISA'] == 'mips':
105 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
106 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
107 if build_env['FULL_SYSTEM']:
108 interrupts = Param.MipsInterrupts(
109 MipsInterrupts(), "Interrupt Controller")
110 elif build_env['TARGET_ISA'] == 'arm':
111 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
112 dtb = Param.ArmTLB(ArmDTB(), "Data TLB")
113 itb = Param.ArmTLB(ArmITB(), "Instruction TLB")
112 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
113 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
114 if build_env['FULL_SYSTEM']:
115 interrupts = Param.ArmInterrupts(
116 ArmInterrupts(), "Interrupt Controller")
117 else:
118 print "Don't know what TLB to use for ISA %s" % \
119 build_env['TARGET_ISA']
120 sys.exit(1)
121

--- 104 unchanged lines hidden --- 		114 if build_env['FULL_SYSTEM']:
115 interrupts = Param.ArmInterrupts(
116 ArmInterrupts(), "Interrupt Controller")
117 else:
118 print "Don't know what TLB to use for ISA %s" % \
119 build_env['TARGET_ISA']
120 sys.exit(1)
121

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