BaseCPU.py (6022:410194bb3049) BaseCPU.py (6023:47b4fcb10c11)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
41 from AlphaTLB import AlphaTLB
41 from AlphaTLB import AlphaDTB, AlphaITB
42 if build_env['FULL_SYSTEM']:
43 from AlphaInterrupts import AlphaInterrupts
44elif build_env['TARGET_ISA'] == 'sparc':
45 from SparcTLB import SparcTLB
46 if build_env['FULL_SYSTEM']:
47 from SparcInterrupts import SparcInterrupts
48elif build_env['TARGET_ISA'] == 'x86':
49 from X86TLB import X86TLB
50 if build_env['FULL_SYSTEM']:
51 from X86LocalApic import X86LocalApic
52elif build_env['TARGET_ISA'] == 'mips':
53 from MipsTLB import MipsTLB
54 if build_env['FULL_SYSTEM']:
55 from MipsInterrupts import MipsInterrupts
56elif build_env['TARGET_ISA'] == 'arm':
42 if build_env['FULL_SYSTEM']:
43 from AlphaInterrupts import AlphaInterrupts
44elif build_env['TARGET_ISA'] == 'sparc':
45 from SparcTLB import SparcTLB
46 if build_env['FULL_SYSTEM']:
47 from SparcInterrupts import SparcInterrupts
48elif build_env['TARGET_ISA'] == 'x86':
49 from X86TLB import X86TLB
50 if build_env['FULL_SYSTEM']:
51 from X86LocalApic import X86LocalApic
52elif build_env['TARGET_ISA'] == 'mips':
53 from MipsTLB import MipsTLB
54 if build_env['FULL_SYSTEM']:
55 from MipsInterrupts import MipsInterrupts
56elif build_env['TARGET_ISA'] == 'arm':
57 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
57 from ArmTLB import ArmDTB
58 if build_env['FULL_SYSTEM']:
59 from ArmInterrupts import ArmInterrupts
60
61class BaseCPU(MemObject):
62 type = 'BaseCPU'
63 abstract = True
64
65 system = Param.System(Parent.any, "system object")

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84
85 if build_env['TARGET_ISA'] == 'sparc':
86 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
87 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
88 if build_env['FULL_SYSTEM']:
89 interrupts = Param.SparcInterrupts(
90 SparcInterrupts(), "Interrupt Controller")
91 elif build_env['TARGET_ISA'] == 'alpha':
58 if build_env['FULL_SYSTEM']:
59 from ArmInterrupts import ArmInterrupts
60
61class BaseCPU(MemObject):
62 type = 'BaseCPU'
63 abstract = True
64
65 system = Param.System(Parent.any, "system object")

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84
85 if build_env['TARGET_ISA'] == 'sparc':
86 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
87 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
88 if build_env['FULL_SYSTEM']:
89 interrupts = Param.SparcInterrupts(
90 SparcInterrupts(), "Interrupt Controller")
91 elif build_env['TARGET_ISA'] == 'alpha':
92 dtb = Param.AlphaTLB(AlphaTLB(size=64), "Data TLB")
93 itb = Param.AlphaTLB(AlphaTLB(size=48), "Instruction TLB")
92 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
93 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
94 if build_env['FULL_SYSTEM']:
95 interrupts = Param.AlphaInterrupts(
96 AlphaInterrupts(), "Interrupt Controller")
97 elif build_env['TARGET_ISA'] == 'x86':
98 dtb = Param.X86TLB(X86TLB(), "Data TLB")
99 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
100 if build_env['FULL_SYSTEM']:
101 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
102 interrupts = \
103 Param.X86LocalApic(_localApic, "Interrupt Controller")
104 elif build_env['TARGET_ISA'] == 'mips':
105 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
106 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
107 if build_env['FULL_SYSTEM']:
108 interrupts = Param.MipsInterrupts(
109 MipsInterrupts(), "Interrupt Controller")
110 elif build_env['TARGET_ISA'] == 'arm':
111 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
94 if build_env['FULL_SYSTEM']:
95 interrupts = Param.AlphaInterrupts(
96 AlphaInterrupts(), "Interrupt Controller")
97 elif build_env['TARGET_ISA'] == 'x86':
98 dtb = Param.X86TLB(X86TLB(), "Data TLB")
99 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
100 if build_env['FULL_SYSTEM']:
101 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
102 interrupts = \
103 Param.X86LocalApic(_localApic, "Interrupt Controller")
104 elif build_env['TARGET_ISA'] == 'mips':
105 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
106 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
107 if build_env['FULL_SYSTEM']:
108 interrupts = Param.MipsInterrupts(
109 MipsInterrupts(), "Interrupt Controller")
110 elif build_env['TARGET_ISA'] == 'arm':
111 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
112 dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
113 itb = Param.ArmITB(ArmITB(), "Instruction TLB")
114 tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
112 dtb = Param.ArmTLB(ArmDTB(), "Data TLB")
113 itb = Param.ArmTLB(ArmITB(), "Instruction TLB")
115 if build_env['FULL_SYSTEM']:
116 interrupts = Param.ArmInterrupts(
117 ArmInterrupts(), "Interrupt Controller")
118 else:
119 print "Don't know what TLB to use for ISA %s" % \
120 build_env['TARGET_ISA']
121 sys.exit(1)
122

--- 104 unchanged lines hidden --- 		114 if build_env['FULL_SYSTEM']:
115 interrupts = Param.ArmInterrupts(
116 ArmInterrupts(), "Interrupt Controller")
117 else:
118 print "Don't know what TLB to use for ISA %s" % \
119 build_env['TARGET_ISA']
120 sys.exit(1)
121

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