BaseCPU.py (5821:2831ae658bfc) BaseCPU.py (6022:410194bb3049)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 24 unchanged lines hidden (view full) ---

33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
41 from AlphaTLB import AlphaDTB, AlphaITB
41 from AlphaTLB import AlphaTLB
42 if build_env['FULL_SYSTEM']:
43 from AlphaInterrupts import AlphaInterrupts
44elif build_env['TARGET_ISA'] == 'sparc':
42 if build_env['FULL_SYSTEM']:
43 from AlphaInterrupts import AlphaInterrupts
44elif build_env['TARGET_ISA'] == 'sparc':
45 from SparcTLB import SparcDTB, SparcITB
45 from SparcTLB import SparcTLB
46 if build_env['FULL_SYSTEM']:
47 from SparcInterrupts import SparcInterrupts
48elif build_env['TARGET_ISA'] == 'x86':
46 if build_env['FULL_SYSTEM']:
47 from SparcInterrupts import SparcInterrupts
48elif build_env['TARGET_ISA'] == 'x86':
49 from X86TLB import X86DTB, X86ITB
49 from X86TLB import X86TLB
50 if build_env['FULL_SYSTEM']:
51 from X86LocalApic import X86LocalApic
52elif build_env['TARGET_ISA'] == 'mips':
50 if build_env['FULL_SYSTEM']:
51 from X86LocalApic import X86LocalApic
52elif build_env['TARGET_ISA'] == 'mips':
53 from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
53 from MipsTLB import MipsTLB
54 if build_env['FULL_SYSTEM']:
55 from MipsInterrupts import MipsInterrupts
56elif build_env['TARGET_ISA'] == 'arm':
57 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
58 if build_env['FULL_SYSTEM']:
59 from ArmInterrupts import ArmInterrupts
60
61class BaseCPU(MemObject):

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78
79 if build_env['FULL_SYSTEM']:
80 profile = Param.Latency('0ns', "trace the kernel stack")
81 do_quiesce = Param.Bool(True, "enable quiesce instructions")
82 else:
83 workload = VectorParam.Process("processes to run")
84
85 if build_env['TARGET_ISA'] == 'sparc':
54 if build_env['FULL_SYSTEM']:
55 from MipsInterrupts import MipsInterrupts
56elif build_env['TARGET_ISA'] == 'arm':
57 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
58 if build_env['FULL_SYSTEM']:
59 from ArmInterrupts import ArmInterrupts
60
61class BaseCPU(MemObject):

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78
79 if build_env['FULL_SYSTEM']:
80 profile = Param.Latency('0ns', "trace the kernel stack")
81 do_quiesce = Param.Bool(True, "enable quiesce instructions")
82 else:
83 workload = VectorParam.Process("processes to run")
84
85 if build_env['TARGET_ISA'] == 'sparc':
86 dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
87 itb = Param.SparcITB(SparcITB(), "Instruction TLB")
86 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
87 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
88 if build_env['FULL_SYSTEM']:
89 interrupts = Param.SparcInterrupts(
90 SparcInterrupts(), "Interrupt Controller")
91 elif build_env['TARGET_ISA'] == 'alpha':
88 if build_env['FULL_SYSTEM']:
89 interrupts = Param.SparcInterrupts(
90 SparcInterrupts(), "Interrupt Controller")
91 elif build_env['TARGET_ISA'] == 'alpha':
92 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
93 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
92 dtb = Param.AlphaTLB(AlphaTLB(size=64), "Data TLB")
93 itb = Param.AlphaTLB(AlphaTLB(size=48), "Instruction TLB")
94 if build_env['FULL_SYSTEM']:
95 interrupts = Param.AlphaInterrupts(
96 AlphaInterrupts(), "Interrupt Controller")
97 elif build_env['TARGET_ISA'] == 'x86':
94 if build_env['FULL_SYSTEM']:
95 interrupts = Param.AlphaInterrupts(
96 AlphaInterrupts(), "Interrupt Controller")
97 elif build_env['TARGET_ISA'] == 'x86':
98 dtb = Param.X86DTB(X86DTB(), "Data TLB")
99 itb = Param.X86ITB(X86ITB(), "Instruction TLB")
98 dtb = Param.X86TLB(X86TLB(), "Data TLB")
99 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
100 if build_env['FULL_SYSTEM']:
101 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
102 interrupts = \
103 Param.X86LocalApic(_localApic, "Interrupt Controller")
104 elif build_env['TARGET_ISA'] == 'mips':
100 if build_env['FULL_SYSTEM']:
101 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
102 interrupts = \
103 Param.X86LocalApic(_localApic, "Interrupt Controller")
104 elif build_env['TARGET_ISA'] == 'mips':
105 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
106 dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
107 itb = Param.MipsITB(MipsITB(), "Instruction TLB")
108 tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
105 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
106 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
109 if build_env['FULL_SYSTEM']:
110 interrupts = Param.MipsInterrupts(
111 MipsInterrupts(), "Interrupt Controller")
112 elif build_env['TARGET_ISA'] == 'arm':
113 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
114 dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
115 itb = Param.ArmITB(ArmITB(), "Instruction TLB")
116 tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")

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108 interrupts = Param.MipsInterrupts(
109 MipsInterrupts(), "Interrupt Controller")
110 elif build_env['TARGET_ISA'] == 'arm':
111 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
112 dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
113 itb = Param.ArmITB(ArmITB(), "Instruction TLB")
114 tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")

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