BaseCPU.py (5648:e8abda6e0980) BaseCPU.py (5651:7f0c8006c3d7)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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139 phase = Param.Latency('0ns', "clock phase")
140
141 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
142
143 _mem_ports = []
144 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
145 _mem_ports = ["itb.walker.port",
146 "dtb.walker.port",
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 130 unchanged lines hidden (view full) ---

139 phase = Param.Latency('0ns', "clock phase")
140
141 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
142
143 _mem_ports = []
144 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
145 _mem_ports = ["itb.walker.port",
146 "dtb.walker.port",
147 "interrupts.pio"]
147 "interrupts.pio",
148 "interrupts.int_port"]
148
149 def connectMemPorts(self, bus):
150 for p in self._mem_ports:
151 if p != 'physmem_port':
152 exec('self.%s = bus.port' % p)
153
154 def addPrivateSplitL1Caches(self, ic, dc):
155 assert(len(self._mem_ports) < 6)

--- 71 unchanged lines hidden --- 		149
150 def connectMemPorts(self, bus):
151 for p in self._mem_ports:
152 if p != 'physmem_port':
153 exec('self.%s = bus.port' % p)
154
155 def addPrivateSplitL1Caches(self, ic, dc):
156 assert(len(self._mem_ports) < 6)

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