BaseCPU.py (5529:9ae69b9cd7fd) BaseCPU.py (5647:b06b49498c79)
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
41 from AlphaTLB import AlphaDTB, AlphaITB
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 25 unchanged lines hidden (view full) ---

34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
41 from AlphaTLB import AlphaDTB, AlphaITB
42 if build_env['FULL_SYSTEM']:
43 from AlphaInterrupts import AlphaInterrupts
42elif build_env['TARGET_ISA'] == 'sparc':
43 from SparcTLB import SparcDTB, SparcITB
44elif build_env['TARGET_ISA'] == 'sparc':
45 from SparcTLB import SparcDTB, SparcITB
46 if build_env['FULL_SYSTEM']:
47 from SparcInterrupts import SparcInterrupts
44elif build_env['TARGET_ISA'] == 'x86':
45 from X86TLB import X86DTB, X86ITB
48elif build_env['TARGET_ISA'] == 'x86':
49 from X86TLB import X86DTB, X86ITB
50 if build_env['FULL_SYSTEM']:
51 from X86LocalApic import X86LocalApic
46elif build_env['TARGET_ISA'] == 'mips':
47 from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
52elif build_env['TARGET_ISA'] == 'mips':
53 from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
54 if build_env['FULL_SYSTEM']:
55 from MipsInterrupts import MipsInterrupts
48elif build_env['TARGET_ISA'] == 'arm':
49 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
56elif build_env['TARGET_ISA'] == 'arm':
57 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
58 if build_env['FULL_SYSTEM']:
59 from ArmInterrupts import ArmInterrupts
50
51class BaseCPU(MemObject):
52 type = 'BaseCPU'
53 abstract = True
54
55 system = Param.System(Parent.any, "system object")
56 cpu_id = Param.Int("CPU identifier")
57 numThreads = Param.Unsigned(1, "number of HW thread contexts")

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69 do_statistics_insts = Param.Bool(True,
70 "enable statistics pseudo instructions")
71 else:
72 workload = VectorParam.Process("processes to run")
73
74 if build_env['TARGET_ISA'] == 'sparc':
75 dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
76 itb = Param.SparcITB(SparcITB(), "Instruction TLB")
60
61class BaseCPU(MemObject):
62 type = 'BaseCPU'
63 abstract = True
64
65 system = Param.System(Parent.any, "system object")
66 cpu_id = Param.Int("CPU identifier")
67 numThreads = Param.Unsigned(1, "number of HW thread contexts")

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79 do_statistics_insts = Param.Bool(True,
80 "enable statistics pseudo instructions")
81 else:
82 workload = VectorParam.Process("processes to run")
83
84 if build_env['TARGET_ISA'] == 'sparc':
85 dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
86 itb = Param.SparcITB(SparcITB(), "Instruction TLB")
87 if build_env['FULL_SYSTEM']:
88 interrupts = Param.SparcInterrupts(
89 SparcInterrupts(), "Interrupt Controller")
77 elif build_env['TARGET_ISA'] == 'alpha':
78 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
79 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
90 elif build_env['TARGET_ISA'] == 'alpha':
91 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
92 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
93 if build_env['FULL_SYSTEM']:
94 interrupts = Param.AlphaInterrupts(
95 AlphaInterrupts(), "Interrupt Controller")
80 elif build_env['TARGET_ISA'] == 'x86':
81 dtb = Param.X86DTB(X86DTB(), "Data TLB")
82 itb = Param.X86ITB(X86ITB(), "Instruction TLB")
96 elif build_env['TARGET_ISA'] == 'x86':
97 dtb = Param.X86DTB(X86DTB(), "Data TLB")
98 itb = Param.X86ITB(X86ITB(), "Instruction TLB")
99 if build_env['FULL_SYSTEM']:
100 interrupts = Param.X86LocalApic(
101 X86LocalApic(), "Interrupt Controller")
83 elif build_env['TARGET_ISA'] == 'mips':
84 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
85 dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
86 itb = Param.MipsITB(MipsITB(), "Instruction TLB")
87 tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
102 elif build_env['TARGET_ISA'] == 'mips':
103 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
104 dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
105 itb = Param.MipsITB(MipsITB(), "Instruction TLB")
106 tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
107 if build_env['FULL_SYSTEM']:
108 interrupts = Param.MipsInterrupts(
109 MipsInterrupts(), "Interrupt Controller")
88 elif build_env['TARGET_ISA'] == 'arm':
89 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
90 dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
91 itb = Param.ArmITB(ArmITB(), "Instruction TLB")
92 tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
110 elif build_env['TARGET_ISA'] == 'arm':
111 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
112 dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
113 itb = Param.ArmITB(ArmITB(), "Instruction TLB")
114 tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
115 if build_env['FULL_SYSTEM']:
116 interrupts = Param.ArmInterrupts(
117 ArmInterrupts(), "Interrupt Controller")
93 else:
94 print "Don't know what TLB to use for ISA %s" % \
95 build_env['TARGET_ISA']
96 sys.exit(1)
97
98 max_insts_all_threads = Param.Counter(0,
99 "terminate when all threads have reached this inst count")
100 max_insts_any_thread = Param.Counter(0,

--- 98 unchanged lines hidden --- 		118 else:
119 print "Don't know what TLB to use for ISA %s" % \
120 build_env['TARGET_ISA']
121 sys.exit(1)
122
123 max_insts_all_threads = Param.Counter(0,
124 "terminate when all threads have reached this inst count")
125 max_insts_any_thread = Param.Counter(0,

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