BaseCPU.py (5335:69d45f5f21a2) | BaseCPU.py (5529:9ae69b9cd7fd) |
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1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 12 unchanged lines hidden (view full) --- 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 | 1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 12 unchanged lines hidden (view full) --- 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 |
29from m5.SimObject import SimObject | 29from MemObject import MemObject |
30from m5.params import * 31from m5.proxy import * 32from m5 import build_env 33from Bus import Bus 34from InstTracer import InstTracer 35from ExeTracer import ExeTracer 36import sys 37 --- 5 unchanged lines hidden (view full) --- 43 from SparcTLB import SparcDTB, SparcITB 44elif build_env['TARGET_ISA'] == 'x86': 45 from X86TLB import X86DTB, X86ITB 46elif build_env['TARGET_ISA'] == 'mips': 47 from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB 48elif build_env['TARGET_ISA'] == 'arm': 49 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB 50 | 30from m5.params import * 31from m5.proxy import * 32from m5 import build_env 33from Bus import Bus 34from InstTracer import InstTracer 35from ExeTracer import ExeTracer 36import sys 37 --- 5 unchanged lines hidden (view full) --- 43 from SparcTLB import SparcDTB, SparcITB 44elif build_env['TARGET_ISA'] == 'x86': 45 from X86TLB import X86DTB, X86ITB 46elif build_env['TARGET_ISA'] == 'mips': 47 from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB 48elif build_env['TARGET_ISA'] == 'arm': 49 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB 50 |
51class BaseCPU(SimObject): | 51class BaseCPU(MemObject): |
52 type = 'BaseCPU' 53 abstract = True 54 55 system = Param.System(Parent.any, "system object") 56 cpu_id = Param.Int("CPU identifier") | 52 type = 'BaseCPU' 53 abstract = True 54 55 system = Param.System(Parent.any, "system object") 56 cpu_id = Param.Int("CPU identifier") |
57 numThreads = Param.Unsigned(1, "number of HW thread contexts") |
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57 | 58 |
59 function_trace = Param.Bool(False, "Enable function trace") 60 function_trace_start = Param.Tick(0, "Cycle to start function trace") 61 62 checker = Param.BaseCPU("checker CPU") 63 |
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58 if build_env['FULL_SYSTEM']: | 64 if build_env['FULL_SYSTEM']: |
65 profile = Param.Latency('0ns', "trace the kernel stack") |
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59 do_quiesce = Param.Bool(True, "enable quiesce instructions") 60 do_checkpoint_insts = Param.Bool(True, 61 "enable checkpoint pseudo instructions") 62 do_statistics_insts = Param.Bool(True, 63 "enable statistics pseudo instructions") 64 else: 65 workload = VectorParam.Process("processes to run") 66 --- 125 unchanged lines hidden --- | 66 do_quiesce = Param.Bool(True, "enable quiesce instructions") 67 do_checkpoint_insts = Param.Bool(True, 68 "enable checkpoint pseudo instructions") 69 do_statistics_insts = Param.Bool(True, 70 "enable statistics pseudo instructions") 71 else: 72 workload = VectorParam.Process("processes to run") 73 --- 125 unchanged lines hidden --- |