BaseCPU.py (5281:61e396061986) BaseCPU.py (5335:69d45f5f21a2)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the

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40if build_env['TARGET_ISA'] == 'alpha':
41 from AlphaTLB import AlphaDTB, AlphaITB
42elif build_env['TARGET_ISA'] == 'sparc':
43 from SparcTLB import SparcDTB, SparcITB
44elif build_env['TARGET_ISA'] == 'x86':
45 from X86TLB import X86DTB, X86ITB
46elif build_env['TARGET_ISA'] == 'mips':
47 from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the

--- 30 unchanged lines hidden (view full) ---

40if build_env['TARGET_ISA'] == 'alpha':
41 from AlphaTLB import AlphaDTB, AlphaITB
42elif build_env['TARGET_ISA'] == 'sparc':
43 from SparcTLB import SparcDTB, SparcITB
44elif build_env['TARGET_ISA'] == 'x86':
45 from X86TLB import X86DTB, X86ITB
46elif build_env['TARGET_ISA'] == 'mips':
47 from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
48elif build_env['TARGET_ISA'] == 'arm':
49 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
48
49class BaseCPU(SimObject):
50 type = 'BaseCPU'
51 abstract = True
52
53 system = Param.System(Parent.any, "system object")
54 cpu_id = Param.Int("CPU identifier")
55

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71 elif build_env['TARGET_ISA'] == 'x86':
72 dtb = Param.X86DTB(X86DTB(), "Data TLB")
73 itb = Param.X86ITB(X86ITB(), "Instruction TLB")
74 elif build_env['TARGET_ISA'] == 'mips':
75 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
76 dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
77 itb = Param.MipsITB(MipsITB(), "Instruction TLB")
78 tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
50
51class BaseCPU(SimObject):
52 type = 'BaseCPU'
53 abstract = True
54
55 system = Param.System(Parent.any, "system object")
56 cpu_id = Param.Int("CPU identifier")
57

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73 elif build_env['TARGET_ISA'] == 'x86':
74 dtb = Param.X86DTB(X86DTB(), "Data TLB")
75 itb = Param.X86ITB(X86ITB(), "Instruction TLB")
76 elif build_env['TARGET_ISA'] == 'mips':
77 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
78 dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
79 itb = Param.MipsITB(MipsITB(), "Instruction TLB")
80 tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
81 elif build_env['TARGET_ISA'] == 'arm':
82 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
83 dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
84 itb = Param.ArmITB(ArmITB(), "Instruction TLB")
85 tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
79 else:
80 print "Don't know what TLB to use for ISA %s" % \
81 build_env['TARGET_ISA']
82 sys.exit(1)
83
84 max_insts_all_threads = Param.Counter(0,
85 "terminate when all threads have reached this inst count")
86 max_insts_any_thread = Param.Counter(0,

--- 98 unchanged lines hidden --- 		86 else:
87 print "Don't know what TLB to use for ISA %s" % \
88 build_env['TARGET_ISA']
89 sys.exit(1)
90
91 max_insts_all_threads = Param.Counter(0,
92 "terminate when all threads have reached this inst count")
93 max_insts_any_thread = Param.Counter(0,

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