BaseCPU.py (5249:49d44a466496) BaseCPU.py (5281:61e396061986)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 87 unchanged lines hidden (view full) ---

96 "defer registration with system (for sampling)")
97
98 clock = Param.Clock('1t', "clock speed")
99 phase = Param.Latency('0ns', "clock phase")
100
101 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
102
103 _mem_ports = []
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 87 unchanged lines hidden (view full) ---

96 "defer registration with system (for sampling)")
97
98 clock = Param.Clock('1t', "clock speed")
99 phase = Param.Latency('0ns', "clock phase")
100
101 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
102
103 _mem_ports = []
104 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
105 _mem_ports = ["itb.walker.port", "dtb.walker.port"]
104
105 def connectMemPorts(self, bus):
106 for p in self._mem_ports:
107 if p != 'physmem_port':
108 exec('self.%s = bus.port' % p)
109
110 def addPrivateSplitL1Caches(self, ic, dc):
106
107 def connectMemPorts(self, bus):
108 for p in self._mem_ports:
109 if p != 'physmem_port':
110 exec('self.%s = bus.port' % p)
111
112 def addPrivateSplitL1Caches(self, ic, dc):
111 assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
113 assert(len(self._mem_ports) < 6)
112 self.icache = ic
113 self.dcache = dc
114 self.icache_port = ic.cpu_side
115 self.dcache_port = dc.cpu_side
116 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
114 self.icache = ic
115 self.dcache = dc
116 self.icache_port = ic.cpu_side
117 self.dcache_port = dc.cpu_side
118 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
119 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
120 self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
117
118 def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
119 self.addPrivateSplitL1Caches(ic, dc)
120 self.toL2Bus = Bus()
121 self.connectMemPorts(self.toL2Bus)
122 self.l2cache = l2c
123 self.l2cache.cpu_side = self.toL2Bus.port
124 self._mem_ports = ['l2cache.mem_side']

--- 56 unchanged lines hidden --- 		121
122 def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
123 self.addPrivateSplitL1Caches(ic, dc)
124 self.toL2Bus = Bus()
125 self.connectMemPorts(self.toL2Bus)
126 self.l2cache = l2c
127 self.l2cache.cpu_side = self.toL2Bus.port
128 self._mem_ports = ['l2cache.mem_side']

--- 56 unchanged lines hidden ---