BaseCPU.py (5237:6c819dbe8045) BaseCPU.py (5245:d94bb8af9f76)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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96 clock = Param.Clock('1t', "clock speed")
97 phase = Param.Latency('0ns', "clock phase")
98
99 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
100
101 _mem_ports = []
102
103 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 87 unchanged lines hidden (view full) ---

96 clock = Param.Clock('1t', "clock speed")
97 phase = Param.Latency('0ns', "clock phase")
98
99 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
100
101 _mem_ports = []
102
103 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
104 itb.walker_port = Port("ITB page table walker port")
105 dtb.walker_port = Port("ITB page table walker port")
106 _mem_ports = ["itb.walker_port", "dtb.walker_port"]
104 _mem_ports = ["itb.walker.port", "dtb.walker.port"]
107
108 def connectMemPorts(self, bus):
109 for p in self._mem_ports:
110 if p != 'physmem_port':
111 exec('self.%s = bus.port' % p)
112
113 def addPrivateSplitL1Caches(self, ic, dc):
114 assert(len(self._mem_ports) < 6)

--- 15 unchanged lines hidden --- 		105
106 def connectMemPorts(self, bus):
107 for p in self._mem_ports:
108 if p != 'physmem_port':
109 exec('self.%s = bus.port' % p)
110
111 def addPrivateSplitL1Caches(self, ic, dc):
112 assert(len(self._mem_ports) < 6)

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