BaseCPU.py (4776:8c8407243a2c) | BaseCPU.py (4968:f1c856d8c460) |
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1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 79 unchanged lines hidden (view full) --- 88 phase = Param.Latency('0ns', "clock phase") 89 90 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 91 92 _mem_ports = [] 93 94 def connectMemPorts(self, bus): 95 for p in self._mem_ports: | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 79 unchanged lines hidden (view full) --- 88 phase = Param.Latency('0ns', "clock phase") 89 90 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 91 92 _mem_ports = [] 93 94 def connectMemPorts(self, bus): 95 for p in self._mem_ports: |
96 exec('self.%s = bus.port' % p) | 96 if p != 'physmem_port': 97 exec('self.%s = bus.port' % p) |
97 98 def addPrivateSplitL1Caches(self, ic, dc): | 98 99 def addPrivateSplitL1Caches(self, ic, dc): |
99 assert(len(self._mem_ports) == 2) | 100 assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3) |
100 self.icache = ic 101 self.dcache = dc 102 self.icache_port = ic.cpu_side 103 self.dcache_port = dc.cpu_side 104 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 105 106 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 107 self.addPrivateSplitL1Caches(ic, dc) 108 self.toL2Bus = Bus() 109 self.connectMemPorts(self.toL2Bus) 110 self.l2cache = l2c 111 self.l2cache.cpu_side = self.toL2Bus.port 112 self._mem_ports = ['l2cache.mem_side'] | 101 self.icache = ic 102 self.dcache = dc 103 self.icache_port = ic.cpu_side 104 self.dcache_port = dc.cpu_side 105 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 106 107 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 108 self.addPrivateSplitL1Caches(ic, dc) 109 self.toL2Bus = Bus() 110 self.connectMemPorts(self.toL2Bus) 111 self.l2cache = l2c 112 self.l2cache.cpu_side = self.toL2Bus.port 113 self._mem_ports = ['l2cache.mem_side'] |