| BaseCPU.py (13711:e796a82c5154) | BaseCPU.py (13892:0182a0601f66) |
|---|---|
| 1# Copyright (c) 2012-2013, 2015-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 38 unchanged lines hidden (view full) --- 47import sys 48 49from m5.SimObject import * 50from m5.defines import buildEnv 51from m5.params import * 52from m5.proxy import * 53from m5.util.fdthelper import * 54 | 1# Copyright (c) 2012-2013, 2015-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 38 unchanged lines hidden (view full) --- 47import sys 48 49from m5.SimObject import * 50from m5.defines import buildEnv 51from m5.params import * 52from m5.proxy import * 53from m5.util.fdthelper import * 54 |
| 55from m5.objects.ClockedObject import ClockedObject |
|
| 55from m5.objects.XBar import L2XBar 56from m5.objects.InstTracer import InstTracer 57from m5.objects.CPUTracers import ExeTracer | 56from m5.objects.XBar import L2XBar 57from m5.objects.InstTracer import InstTracer 58from m5.objects.CPUTracers import ExeTracer |
| 58from m5.objects.MemObject import MemObject | |
| 59from m5.objects.SubSystem import SubSystem 60from m5.objects.ClockDomain import * 61from m5.objects.Platform import Platform 62 63default_tracer = ExeTracer() 64 65if buildEnv['TARGET_ISA'] == 'alpha': 66 from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB --- 27 unchanged lines hidden (view full) --- 94 from m5.objects.PowerISA import PowerISA 95 default_isa_class = PowerISA 96elif buildEnv['TARGET_ISA'] == 'riscv': 97 from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB 98 from m5.objects.RiscvInterrupts import RiscvInterrupts 99 from m5.objects.RiscvISA import RiscvISA 100 default_isa_class = RiscvISA 101 | 59from m5.objects.SubSystem import SubSystem 60from m5.objects.ClockDomain import * 61from m5.objects.Platform import Platform 62 63default_tracer = ExeTracer() 64 65if buildEnv['TARGET_ISA'] == 'alpha': 66 from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB --- 27 unchanged lines hidden (view full) --- 94 from m5.objects.PowerISA import PowerISA 95 default_isa_class = PowerISA 96elif buildEnv['TARGET_ISA'] == 'riscv': 97 from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB 98 from m5.objects.RiscvInterrupts import RiscvInterrupts 99 from m5.objects.RiscvISA import RiscvISA 100 default_isa_class = RiscvISA 101 |
| 102class BaseCPU(MemObject): | 102class BaseCPU(ClockedObject): |
| 103 type = 'BaseCPU' 104 abstract = True 105 cxx_header = "cpu/base.hh" 106 107 cxx_exports = [ 108 PyBindMethod("switchOut"), 109 PyBindMethod("takeOverFrom"), 110 PyBindMethod("switchedOut"), --- 266 unchanged lines hidden --- | 103 type = 'BaseCPU' 104 abstract = True 105 cxx_header = "cpu/base.hh" 106 107 cxx_exports = [ 108 PyBindMethod("switchOut"), 109 PyBindMethod("takeOverFrom"), 110 PyBindMethod("switchedOut"), --- 266 unchanged lines hidden --- |