| BaseCPU.py (12434:715d029898f4) | BaseCPU.py (12440:e028053ee1fc) |
|---|---|
| 1# Copyright (c) 2012-2013, 2015-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 285 unchanged lines hidden (view full) --- 294 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 295 296 # Checker doesn't need its own tlb caches because it does 297 # functional accesses only 298 if self.checker != NULL: 299 self._cached_ports += ["checker.itb.walker.port", \ 300 "checker.dtb.walker.port"] 301 | 1# Copyright (c) 2012-2013, 2015-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 285 unchanged lines hidden (view full) --- 294 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 295 296 # Checker doesn't need its own tlb caches because it does 297 # functional accesses only 298 if self.checker != NULL: 299 self._cached_ports += ["checker.itb.walker.port", \ 300 "checker.dtb.walker.port"] 301 |
| 302 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): | 302 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, 303 xbar=None): |
| 303 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) | 304 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) |
| 304 self.toL2Bus = L2XBar() | 305 self.toL2Bus = xbar if xbar else L2XBar() |
| 305 self.connectCachedPorts(self.toL2Bus) 306 self.l2cache = l2c 307 self.toL2Bus.master = self.l2cache.cpu_side 308 self._cached_ports = ['l2cache.mem_side'] 309 310 def createThreads(self): 311 # If no ISAs have been created, assume that the user wants the 312 # default ISA. 313 if len(self.isa) == 0: 314 self.isa = [ default_isa_class() for i in xrange(self.numThreads) ] 315 else: 316 if len(self.isa) != int(self.numThreads): 317 raise RuntimeError("Number of ISA instances doesn't " 318 "match thread count") 319 if self.checker != NULL: 320 self.checker.createThreads() 321 322 def addCheckerCpu(self): 323 pass | 306 self.connectCachedPorts(self.toL2Bus) 307 self.l2cache = l2c 308 self.toL2Bus.master = self.l2cache.cpu_side 309 self._cached_ports = ['l2cache.mem_side'] 310 311 def createThreads(self): 312 # If no ISAs have been created, assume that the user wants the 313 # default ISA. 314 if len(self.isa) == 0: 315 self.isa = [ default_isa_class() for i in xrange(self.numThreads) ] 316 else: 317 if len(self.isa) != int(self.numThreads): 318 raise RuntimeError("Number of ISA instances doesn't " 319 "match thread count") 320 if self.checker != NULL: 321 self.checker.createThreads() 322 323 def addCheckerCpu(self): 324 pass |