BaseCPU.py (12277:e6455b421c4b) BaseCPU.py (12325:48e41e644187)
1# Copyright (c) 2012-2013, 2015-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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55from ClockDomain import *
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60 from AlphaTLB import AlphaDTB, AlphaITB
61 from AlphaInterrupts import AlphaInterrupts
62 from AlphaISA import AlphaISA
1# Copyright (c) 2012-2013, 2015-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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55from ClockDomain import *
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60 from AlphaTLB import AlphaDTB, AlphaITB
61 from AlphaInterrupts import AlphaInterrupts
62 from AlphaISA import AlphaISA
63 isa_class = AlphaISA
63 default_isa_class = AlphaISA
64elif buildEnv['TARGET_ISA'] == 'sparc':
65 from SparcTLB import SparcTLB
66 from SparcInterrupts import SparcInterrupts
67 from SparcISA import SparcISA
64elif buildEnv['TARGET_ISA'] == 'sparc':
65 from SparcTLB import SparcTLB
66 from SparcInterrupts import SparcInterrupts
67 from SparcISA import SparcISA
68 isa_class = SparcISA
68 default_isa_class = SparcISA
69elif buildEnv['TARGET_ISA'] == 'x86':
70 from X86TLB import X86TLB
71 from X86LocalApic import X86LocalApic
72 from X86ISA import X86ISA
69elif buildEnv['TARGET_ISA'] == 'x86':
70 from X86TLB import X86TLB
71 from X86LocalApic import X86LocalApic
72 from X86ISA import X86ISA
73 isa_class = X86ISA
73 default_isa_class = X86ISA
74elif buildEnv['TARGET_ISA'] == 'mips':
75 from MipsTLB import MipsTLB
76 from MipsInterrupts import MipsInterrupts
77 from MipsISA import MipsISA
74elif buildEnv['TARGET_ISA'] == 'mips':
75 from MipsTLB import MipsTLB
76 from MipsInterrupts import MipsInterrupts
77 from MipsISA import MipsISA
78 isa_class = MipsISA
78 default_isa_class = MipsISA
79elif buildEnv['TARGET_ISA'] == 'arm':
80 from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
81 from ArmInterrupts import ArmInterrupts
82 from ArmISA import ArmISA
79elif buildEnv['TARGET_ISA'] == 'arm':
80 from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
81 from ArmInterrupts import ArmInterrupts
82 from ArmISA import ArmISA
83 isa_class = ArmISA
83 default_isa_class = ArmISA
84elif buildEnv['TARGET_ISA'] == 'power':
85 from PowerTLB import PowerTLB
86 from PowerInterrupts import PowerInterrupts
87 from PowerISA import PowerISA
84elif buildEnv['TARGET_ISA'] == 'power':
85 from PowerTLB import PowerTLB
86 from PowerInterrupts import PowerInterrupts
87 from PowerISA import PowerISA
88 isa_class = PowerISA
88 default_isa_class = PowerISA
89elif buildEnv['TARGET_ISA'] == 'riscv':
90 from RiscvTLB import RiscvTLB
91 from RiscvInterrupts import RiscvInterrupts
92 from RiscvISA import RiscvISA
89elif buildEnv['TARGET_ISA'] == 'riscv':
90 from RiscvTLB import RiscvTLB
91 from RiscvInterrupts import RiscvInterrupts
92 from RiscvISA import RiscvISA
93 isa_class = RiscvISA
93 default_isa_class = RiscvISA
94
95class BaseCPU(MemObject):
96 type = 'BaseCPU'
97 abstract = True
98 cxx_header = "cpu/base.hh"
99
100 cxx_exports = [
101 PyBindMethod("switchOut"),

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162
163 workload = VectorParam.Process([], "processes to run")
164
165 if buildEnv['TARGET_ISA'] == 'sparc':
166 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
167 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
168 interrupts = VectorParam.SparcInterrupts(
169 [], "Interrupt Controller")
94
95class BaseCPU(MemObject):
96 type = 'BaseCPU'
97 abstract = True
98 cxx_header = "cpu/base.hh"
99
100 cxx_exports = [
101 PyBindMethod("switchOut"),

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162
163 workload = VectorParam.Process([], "processes to run")
164
165 if buildEnv['TARGET_ISA'] == 'sparc':
166 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
167 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
168 interrupts = VectorParam.SparcInterrupts(
169 [], "Interrupt Controller")
170 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
170 isa = VectorParam.SparcISA([], "ISA instance")
171 elif buildEnv['TARGET_ISA'] == 'alpha':
172 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
173 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
174 interrupts = VectorParam.AlphaInterrupts(
175 [], "Interrupt Controller")
171 elif buildEnv['TARGET_ISA'] == 'alpha':
172 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
173 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
174 interrupts = VectorParam.AlphaInterrupts(
175 [], "Interrupt Controller")
176 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
176 isa = VectorParam.AlphaISA([], "ISA instance")
177 elif buildEnv['TARGET_ISA'] == 'x86':
178 dtb = Param.X86TLB(X86TLB(), "Data TLB")
179 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
180 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
177 elif buildEnv['TARGET_ISA'] == 'x86':
178 dtb = Param.X86TLB(X86TLB(), "Data TLB")
179 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
180 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
181 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
181 isa = VectorParam.X86ISA([], "ISA instance")
182 elif buildEnv['TARGET_ISA'] == 'mips':
183 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
184 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
185 interrupts = VectorParam.MipsInterrupts(
186 [], "Interrupt Controller")
182 elif buildEnv['TARGET_ISA'] == 'mips':
183 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
184 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
185 interrupts = VectorParam.MipsInterrupts(
186 [], "Interrupt Controller")
187 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
187 isa = VectorParam.MipsISA([], "ISA instance")
188 elif buildEnv['TARGET_ISA'] == 'arm':
189 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
190 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
191 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
192 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
193 interrupts = VectorParam.ArmInterrupts(
194 [], "Interrupt Controller")
188 elif buildEnv['TARGET_ISA'] == 'arm':
189 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
190 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
191 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
192 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
193 interrupts = VectorParam.ArmInterrupts(
194 [], "Interrupt Controller")
195 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
195 isa = VectorParam.ArmISA([], "ISA instance")
196 elif buildEnv['TARGET_ISA'] == 'power':
197 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
198 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
199 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
200 interrupts = VectorParam.PowerInterrupts(
201 [], "Interrupt Controller")
196 elif buildEnv['TARGET_ISA'] == 'power':
197 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
198 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
199 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
200 interrupts = VectorParam.PowerInterrupts(
201 [], "Interrupt Controller")
202 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
202 isa = VectorParam.PowerISA([], "ISA instance")
203 elif buildEnv['TARGET_ISA'] == 'riscv':
204 dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
205 itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
206 interrupts = VectorParam.RiscvInterrupts(
207 [], "Interrupt Controller")
203 elif buildEnv['TARGET_ISA'] == 'riscv':
204 dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
205 itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
206 interrupts = VectorParam.RiscvInterrupts(
207 [], "Interrupt Controller")
208 isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
208 isa = VectorParam.RiscvISA([], "ISA instance")
209 else:
210 print "Don't know what TLB to use for ISA %s" % \
211 buildEnv['TARGET_ISA']
212 sys.exit(1)
213
214 max_insts_all_threads = Param.Counter(0,
215 "terminate when all threads have reached this inst count")
216 max_insts_any_thread = Param.Counter(0,

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314 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
315 self.toL2Bus = L2XBar()
316 self.connectCachedPorts(self.toL2Bus)
317 self.l2cache = l2c
318 self.toL2Bus.master = self.l2cache.cpu_side
319 self._cached_ports = ['l2cache.mem_side']
320
321 def createThreads(self):
209 else:
210 print "Don't know what TLB to use for ISA %s" % \
211 buildEnv['TARGET_ISA']
212 sys.exit(1)
213
214 max_insts_all_threads = Param.Counter(0,
215 "terminate when all threads have reached this inst count")
216 max_insts_any_thread = Param.Counter(0,

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314 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
315 self.toL2Bus = L2XBar()
316 self.connectCachedPorts(self.toL2Bus)
317 self.l2cache = l2c
318 self.toL2Bus.master = self.l2cache.cpu_side
319 self._cached_ports = ['l2cache.mem_side']
320
321 def createThreads(self):
322 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
322 # If no ISAs have been created, assume that the user wants the
323 # default ISA.
324 if len(self.isa) == 0:
325 self.isa = [ default_isa_class() for i in xrange(self.numThreads) ]
326 else:
327 if len(self.isa) != int(self.numThreads):
328 raise RuntimeError("Number of ISA instances doesn't "
329 "match thread count")
323 if self.checker != NULL:
324 self.checker.createThreads()
325
326 def addCheckerCpu(self):
327 pass
330 if self.checker != NULL:
331 self.checker.createThreads()
332
333 def addCheckerCpu(self):
334 pass