BaseCPU.py (11877:5ea85692a53e) BaseCPU.py (11988:665cd5f8b52b)
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.SimObject import *
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from XBar import L2XBar
51from InstTracer import InstTracer
52from CPUTracers import ExeTracer
53from MemObject import MemObject

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91 from RiscvISA import RiscvISA
92 isa_class = RiscvISA
93
94class BaseCPU(MemObject):
95 type = 'BaseCPU'
96 abstract = True
97 cxx_header = "cpu/base.hh"
98
47from m5.defines import buildEnv
48from m5.params import *
49from m5.proxy import *
50
51from XBar import L2XBar
52from InstTracer import InstTracer
53from CPUTracers import ExeTracer
54from MemObject import MemObject

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92 from RiscvISA import RiscvISA
93 isa_class = RiscvISA
94
95class BaseCPU(MemObject):
96 type = 'BaseCPU'
97 abstract = True
98 cxx_header = "cpu/base.hh"
99
99 @classmethod
100 def export_methods(cls, code):
101 code('''
102 void switchOut();
103 void takeOverFrom(BaseCPU *cpu);
104 bool switchedOut();
105 void flushTLBs();
106 Counter totalInsts();
107 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
108 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
109 uint64_t getCurrentInstCount(ThreadID tid);
110''')
100 cxx_exports = [
101 PyBindMethod("switchOut"),
102 PyBindMethod("takeOverFrom"),
103 PyBindMethod("switchedOut"),
104 PyBindMethod("flushTLBs"),
105 PyBindMethod("totalInsts"),
106 PyBindMethod("scheduleInstStop"),
107 PyBindMethod("scheduleLoadStop"),
108 PyBindMethod("getCurrentInstCount"),
109 ]
111
112 @classmethod
113 def memory_mode(cls):
114 """Which memory mode does this CPU require?"""
115 return 'invalid'
116
117 @classmethod
118 def require_caches(cls):

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111 @classmethod
112 def memory_mode(cls):
113 """Which memory mode does this CPU require?"""
114 return 'invalid'
115
116 @classmethod
117 def require_caches(cls):

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