BaseCPU.py (11415:d6c8016a9a03) BaseCPU.py (11723:0596db108c53)
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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80 from ArmInterrupts import ArmInterrupts
81 from ArmISA import ArmISA
82 isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84 from PowerTLB import PowerTLB
85 from PowerInterrupts import PowerInterrupts
86 from PowerISA import PowerISA
87 isa_class = PowerISA
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 71 unchanged lines hidden (view full) ---

80 from ArmInterrupts import ArmInterrupts
81 from ArmISA import ArmISA
82 isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84 from PowerTLB import PowerTLB
85 from PowerInterrupts import PowerInterrupts
86 from PowerISA import PowerISA
87 isa_class = PowerISA
88elif buildEnv['TARGET_ISA'] == 'riscv':
89 from RiscvTLB import RiscvTLB
90 from RiscvInterrupts import RiscvInterrupts
91 from RiscvISA import RiscvISA
92 isa_class = RiscvISA
88
89class BaseCPU(MemObject):
90 type = 'BaseCPU'
91 abstract = True
92 cxx_header = "cpu/base.hh"
93
94 @classmethod
95 def export_methods(cls, code):

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180 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
181 elif buildEnv['TARGET_ISA'] == 'power':
182 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
183 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
184 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
185 interrupts = VectorParam.PowerInterrupts(
186 [], "Interrupt Controller")
187 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
93
94class BaseCPU(MemObject):
95 type = 'BaseCPU'
96 abstract = True
97 cxx_header = "cpu/base.hh"
98
99 @classmethod
100 def export_methods(cls, code):

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185 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
186 elif buildEnv['TARGET_ISA'] == 'power':
187 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
188 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
189 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
190 interrupts = VectorParam.PowerInterrupts(
191 [], "Interrupt Controller")
192 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
193 elif buildEnv['TARGET_ISA'] == 'riscv':
194 dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
195 itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
196 interrupts = VectorParam.RiscvInterrupts(
197 [], "Interrupt Controller")
198 isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
188 else:
189 print "Don't know what TLB to use for ISA %s" % \
190 buildEnv['TARGET_ISA']
191 sys.exit(1)
192
193 max_insts_all_threads = Param.Counter(0,
194 "terminate when all threads have reached this inst count")
195 max_insts_any_thread = Param.Counter(0,

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237 for i in xrange(self.numThreads)]
238 _localApic = self.interrupts
239 elif buildEnv['TARGET_ISA'] == 'mips':
240 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
241 elif buildEnv['TARGET_ISA'] == 'arm':
242 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
243 elif buildEnv['TARGET_ISA'] == 'power':
244 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
199 else:
200 print "Don't know what TLB to use for ISA %s" % \
201 buildEnv['TARGET_ISA']
202 sys.exit(1)
203
204 max_insts_all_threads = Param.Counter(0,
205 "terminate when all threads have reached this inst count")
206 max_insts_any_thread = Param.Counter(0,

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248 for i in xrange(self.numThreads)]
249 _localApic = self.interrupts
250 elif buildEnv['TARGET_ISA'] == 'mips':
251 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
252 elif buildEnv['TARGET_ISA'] == 'arm':
253 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
254 elif buildEnv['TARGET_ISA'] == 'power':
255 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
256 elif buildEnv['TARGET_ISA'] == 'riscv':
257 self.interrupts = \
258 [RiscvInterrupts() for i in xrange(self.numThreads)]
245 else:
246 print "Don't know what Interrupt Controller to use for ISA %s" % \
247 buildEnv['TARGET_ISA']
248 sys.exit(1)
249
250 def connectCachedPorts(self, bus):
251 for p in self._cached_ports:
252 exec('self.%s = bus.slave' % p)

--- 51 unchanged lines hidden --- 		259 else:
260 print "Don't know what Interrupt Controller to use for ISA %s" % \
261 buildEnv['TARGET_ISA']
262 sys.exit(1)
263
264 def connectCachedPorts(self, bus):
265 for p in self._cached_ports:
266 exec('self.%s = bus.slave' % p)

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