BaseCPU.py (10720:67b3e74de9ae) BaseCPU.py (11150:a8a64cca231b)
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 135 unchanged lines hidden (view full) ---

144 profile = Param.Latency('0ns', "trace the kernel stack")
145 do_quiesce = Param.Bool(True, "enable quiesce instructions")
146
147 workload = VectorParam.Process([], "processes to run")
148
149 if buildEnv['TARGET_ISA'] == 'sparc':
150 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
151 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 135 unchanged lines hidden (view full) ---

144 profile = Param.Latency('0ns', "trace the kernel stack")
145 do_quiesce = Param.Bool(True, "enable quiesce instructions")
146
147 workload = VectorParam.Process([], "processes to run")
148
149 if buildEnv['TARGET_ISA'] == 'sparc':
150 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
151 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
152 interrupts = Param.SparcInterrupts(
153 NULL, "Interrupt Controller")
152 interrupts = VectorParam.SparcInterrupts(
153 [], "Interrupt Controller")
154 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
155 elif buildEnv['TARGET_ISA'] == 'alpha':
156 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
157 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
154 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
155 elif buildEnv['TARGET_ISA'] == 'alpha':
156 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
157 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
158 interrupts = Param.AlphaInterrupts(
159 NULL, "Interrupt Controller")
158 interrupts = VectorParam.AlphaInterrupts(
159 [], "Interrupt Controller")
160 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
161 elif buildEnv['TARGET_ISA'] == 'x86':
162 dtb = Param.X86TLB(X86TLB(), "Data TLB")
163 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
160 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
161 elif buildEnv['TARGET_ISA'] == 'x86':
162 dtb = Param.X86TLB(X86TLB(), "Data TLB")
163 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
164 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
164 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
165 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
166 elif buildEnv['TARGET_ISA'] == 'mips':
167 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
168 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
165 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
166 elif buildEnv['TARGET_ISA'] == 'mips':
167 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
168 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
169 interrupts = Param.MipsInterrupts(
170 NULL, "Interrupt Controller")
169 interrupts = VectorParam.MipsInterrupts(
170 [], "Interrupt Controller")
171 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
172 elif buildEnv['TARGET_ISA'] == 'arm':
173 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
174 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
175 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
176 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
171 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
172 elif buildEnv['TARGET_ISA'] == 'arm':
173 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
174 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
175 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
176 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
177 interrupts = Param.ArmInterrupts(
178 NULL, "Interrupt Controller")
177 interrupts = VectorParam.ArmInterrupts(
178 [], "Interrupt Controller")
179 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
180 elif buildEnv['TARGET_ISA'] == 'power':
181 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
182 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
183 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
179 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
180 elif buildEnv['TARGET_ISA'] == 'power':
181 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
182 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
183 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
184 interrupts = Param.PowerInterrupts(
185 NULL, "Interrupt Controller")
184 interrupts = VectorParam.PowerInterrupts(
185 [], "Interrupt Controller")
186 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
187 else:
188 print "Don't know what TLB to use for ISA %s" % \
189 buildEnv['TARGET_ISA']
190 sys.exit(1)
191
192 max_insts_all_threads = Param.Counter(0,
193 "terminate when all threads have reached this inst count")

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213 _cached_ports = ['icache_port', 'dcache_port']
214
215 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
216 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
217
218 _uncached_slave_ports = []
219 _uncached_master_ports = []
220 if buildEnv['TARGET_ISA'] == 'x86':
186 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
187 else:
188 print "Don't know what TLB to use for ISA %s" % \
189 buildEnv['TARGET_ISA']
190 sys.exit(1)
191
192 max_insts_all_threads = Param.Counter(0,
193 "terminate when all threads have reached this inst count")

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213 _cached_ports = ['icache_port', 'dcache_port']
214
215 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
216 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
217
218 _uncached_slave_ports = []
219 _uncached_master_ports = []
220 if buildEnv['TARGET_ISA'] == 'x86':
221 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
222 _uncached_master_ports += ["interrupts.int_master"]
221 _uncached_slave_ports += ["interrupts[0].pio",
222 "interrupts[0].int_slave"]
223 _uncached_master_ports += ["interrupts[0].int_master"]
223
224 def createInterruptController(self):
225 if buildEnv['TARGET_ISA'] == 'sparc':
224
225 def createInterruptController(self):
226 if buildEnv['TARGET_ISA'] == 'sparc':
226 self.interrupts = SparcInterrupts()
227 self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
227 elif buildEnv['TARGET_ISA'] == 'alpha':
228 elif buildEnv['TARGET_ISA'] == 'alpha':
228 self.interrupts = AlphaInterrupts()
229 self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
229 elif buildEnv['TARGET_ISA'] == 'x86':
230 self.apic_clk_domain = DerivedClockDomain(clk_domain =
231 Parent.clk_domain,
232 clk_divider = 16)
230 elif buildEnv['TARGET_ISA'] == 'x86':
231 self.apic_clk_domain = DerivedClockDomain(clk_domain =
232 Parent.clk_domain,
233 clk_divider = 16)
233 self.interrupts = X86LocalApic(clk_domain = self.apic_clk_domain,
234 self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
234 pio_addr=0x2000000000000000)
235 pio_addr=0x2000000000000000)
236 for i in xrange(self.numThreads)]
235 _localApic = self.interrupts
236 elif buildEnv['TARGET_ISA'] == 'mips':
237 _localApic = self.interrupts
238 elif buildEnv['TARGET_ISA'] == 'mips':
237 self.interrupts = MipsInterrupts()
239 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
238 elif buildEnv['TARGET_ISA'] == 'arm':
240 elif buildEnv['TARGET_ISA'] == 'arm':
239 self.interrupts = ArmInterrupts()
241 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
240 elif buildEnv['TARGET_ISA'] == 'power':
242 elif buildEnv['TARGET_ISA'] == 'power':
241 self.interrupts = PowerInterrupts()
243 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
242 else:
243 print "Don't know what Interrupt Controller to use for ISA %s" % \
244 buildEnv['TARGET_ISA']
245 sys.exit(1)
246
247 def connectCachedPorts(self, bus):
248 for p in self._cached_ports:
249 exec('self.%s = bus.slave' % p)

--- 51 unchanged lines hidden --- 		244 else:
245 print "Don't know what Interrupt Controller to use for ISA %s" % \
246 buildEnv['TARGET_ISA']
247 sys.exit(1)
248
249 def connectCachedPorts(self, bus):
250 for p in self._cached_ports:
251 exec('self.%s = bus.slave' % p)

--- 51 unchanged lines hidden ---