BaseCPU.py (10663:fae54a666162) BaseCPU.py (10717:4f8c1bd6fdb8)
1# Copyright (c) 2012-2013 ARM Limited
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 199 unchanged lines hidden (view full) ---

209 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
210
211 icache_port = MasterPort("Instruction Port")
212 dcache_port = MasterPort("Data Port")
213 _cached_ports = ['icache_port', 'dcache_port']
214
215 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
216 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 199 unchanged lines hidden (view full) ---

209 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
210
211 icache_port = MasterPort("Instruction Port")
212 dcache_port = MasterPort("Data Port")
213 _cached_ports = ['icache_port', 'dcache_port']
214
215 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
216 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
217 if buildEnv['TARGET_ISA'] in ['arm']:
218 _cached_ports += ["istage2_mmu.stage2_tlb.walker.port",
219 "dstage2_mmu.stage2_tlb.walker.port"]
220
221 _uncached_slave_ports = []
222 _uncached_master_ports = []
223 if buildEnv['TARGET_ISA'] == 'x86':
224 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
225 _uncached_master_ports += ["interrupts.int_master"]
226
227 def createInterruptController(self):

--- 40 unchanged lines hidden (view full) ---

268 self.dcache = dc
269 self.icache_port = ic.cpu_side
270 self.dcache_port = dc.cpu_side
271 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
272 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
273 if iwc and dwc:
274 self.itb_walker_cache = iwc
275 self.dtb_walker_cache = dwc
217
218 _uncached_slave_ports = []
219 _uncached_master_ports = []
220 if buildEnv['TARGET_ISA'] == 'x86':
221 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
222 _uncached_master_ports += ["interrupts.int_master"]
223
224 def createInterruptController(self):

--- 40 unchanged lines hidden (view full) ---

265 self.dcache = dc
266 self.icache_port = ic.cpu_side
267 self.dcache_port = dc.cpu_side
268 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
269 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
270 if iwc and dwc:
271 self.itb_walker_cache = iwc
272 self.dtb_walker_cache = dwc
276 if buildEnv['TARGET_ISA'] in ['arm']:
277 self.itb_walker_cache_bus = CoherentXBar()
278 self.dtb_walker_cache_bus = CoherentXBar()
279 self.itb_walker_cache_bus.master = iwc.cpu_side
280 self.dtb_walker_cache_bus.master = dwc.cpu_side
281 self.itb.walker.port = self.itb_walker_cache_bus.slave
282 self.dtb.walker.port = self.dtb_walker_cache_bus.slave
283 self.istage2_mmu.stage2_tlb.walker.port = self.itb_walker_cache_bus.slave
284 self.dstage2_mmu.stage2_tlb.walker.port = self.dtb_walker_cache_bus.slave
285 else:
286 self.itb.walker.port = iwc.cpu_side
287 self.dtb.walker.port = dwc.cpu_side
273 self.itb.walker.port = iwc.cpu_side
274 self.dtb.walker.port = dwc.cpu_side
288 self._cached_ports += ["itb_walker_cache.mem_side", \
289 "dtb_walker_cache.mem_side"]
290 else:
291 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
292
275 self._cached_ports += ["itb_walker_cache.mem_side", \
276 "dtb_walker_cache.mem_side"]
277 else:
278 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
279
293 if buildEnv['TARGET_ISA'] in ['arm']:
294 self._cached_ports += ["istage2_mmu.stage2_tlb.walker.port", \
295 "dstage2_mmu.stage2_tlb.walker.port"]
296
297 # Checker doesn't need its own tlb caches because it does
298 # functional accesses only
299 if self.checker != NULL:
300 self._cached_ports += ["checker.itb.walker.port", \
301 "checker.dtb.walker.port"]
280 # Checker doesn't need its own tlb caches because it does
281 # functional accesses only
282 if self.checker != NULL:
283 self._cached_ports += ["checker.itb.walker.port", \
284 "checker.dtb.walker.port"]
302 if buildEnv['TARGET_ISA'] in ['arm']:
303 self._cached_ports += ["checker.istage2_mmu.stage2_tlb.walker.port", \
304 "checker.dstage2_mmu.stage2_tlb.walker.port"]
305
306 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
307 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
308 # Set a width of 32 bytes (256-bits), which is four times that
309 # of the default bus. The clock of the CPU is inherited by
310 # default.
311 self.toL2Bus = CoherentXBar(width = 32)
312 self.connectCachedPorts(self.toL2Bus)
313 self.l2cache = l2c
314 self.toL2Bus.master = self.l2cache.cpu_side
315 self._cached_ports = ['l2cache.mem_side']
316
317 def createThreads(self):
318 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
319 if self.checker != NULL:
320 self.checker.createThreads()
321
322 def addCheckerCpu(self):
323 pass
285
286 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
287 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
288 # Set a width of 32 bytes (256-bits), which is four times that
289 # of the default bus. The clock of the CPU is inherited by
290 # default.
291 self.toL2Bus = CoherentXBar(width = 32)
292 self.connectCachedPorts(self.toL2Bus)
293 self.l2cache = l2c
294 self.toL2Bus.master = self.l2cache.cpu_side
295 self._cached_ports = ['l2cache.mem_side']
296
297 def createThreads(self):
298 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
299 if self.checker != NULL:
300 self.checker.createThreads()
301
302 def addCheckerCpu(self):
303 pass