| BaseCPU.py (10405:7a618c07e663) | BaseCPU.py (10663:fae54a666162) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 35 unchanged lines hidden (view full) --- 44import sys 45 46from m5.defines import buildEnv 47from m5.params import * 48from m5.proxy import * 49 50from XBar import CoherentXBar 51from InstTracer import InstTracer | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 35 unchanged lines hidden (view full) --- 44import sys 45 46from m5.defines import buildEnv 47from m5.params import * 48from m5.proxy import * 49 50from XBar import CoherentXBar 51from InstTracer import InstTracer |
| 52from ExeTracer import ExeTracer | 52from CPUTracers import ExeTracer |
| 53from MemObject import MemObject 54from ClockDomain import * 55 56default_tracer = ExeTracer() 57 58if buildEnv['TARGET_ISA'] == 'alpha': 59 from AlphaTLB import AlphaDTB, AlphaITB 60 from AlphaInterrupts import AlphaInterrupts --- 263 unchanged lines hidden --- | 53from MemObject import MemObject 54from ClockDomain import * 55 56default_tracer = ExeTracer() 57 58if buildEnv['TARGET_ISA'] == 'alpha': 59 from AlphaTLB import AlphaDTB, AlphaITB 60 from AlphaInterrupts import AlphaInterrupts --- 263 unchanged lines hidden --- |