1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38from InstTracer import InstTracer 39from ExeTracer import ExeTracer 40from MemObject import MemObject 41 42default_tracer = ExeTracer() 43 44if buildEnv['TARGET_ISA'] == 'alpha': 45 from AlphaTLB import AlphaDTB, AlphaITB |
46 from AlphaInterrupts import AlphaInterrupts |
47elif buildEnv['TARGET_ISA'] == 'sparc': 48 from SparcTLB import SparcTLB |
49 from SparcInterrupts import SparcInterrupts |
50elif buildEnv['TARGET_ISA'] == 'x86': 51 from X86TLB import X86TLB |
52 from X86LocalApic import X86LocalApic |
53elif buildEnv['TARGET_ISA'] == 'mips': 54 from MipsTLB import MipsTLB |
55 from MipsInterrupts import MipsInterrupts |
56elif buildEnv['TARGET_ISA'] == 'arm': 57 from ArmTLB import ArmTLB |
58 from ArmInterrupts import ArmInterrupts |
59elif buildEnv['TARGET_ISA'] == 'power': 60 from PowerTLB import PowerTLB |
61 from PowerInterrupts import PowerInterrupts |
62 63class BaseCPU(MemObject): 64 type = 'BaseCPU' 65 abstract = True 66 67 system = Param.System(Parent.any, "system object") 68 cpu_id = Param.Int(-1, "CPU identifier") 69 numThreads = Param.Unsigned(1, "number of HW thread contexts") --- 12 unchanged lines hidden (view full) --- 82 profile = Param.Latency('0ns', "trace the kernel stack") 83 do_quiesce = Param.Bool(True, "enable quiesce instructions") 84 else: 85 workload = VectorParam.Process("processes to run") 86 87 if buildEnv['TARGET_ISA'] == 'sparc': 88 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 89 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") |
90 interrupts = Param.SparcInterrupts( |
91 SparcInterrupts(), "Interrupt Controller") 92 elif buildEnv['TARGET_ISA'] == 'alpha': 93 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 94 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") |
95 interrupts = Param.AlphaInterrupts( |
96 AlphaInterrupts(), "Interrupt Controller") 97 elif buildEnv['TARGET_ISA'] == 'x86': 98 dtb = Param.X86TLB(X86TLB(), "Data TLB") 99 itb = Param.X86TLB(X86TLB(), "Instruction TLB") |
100 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 101 interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") |
102 elif buildEnv['TARGET_ISA'] == 'mips': 103 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 104 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") |
105 interrupts = Param.MipsInterrupts( 106 MipsInterrupts(), "Interrupt Controller") |
107 elif buildEnv['TARGET_ISA'] == 'arm': 108 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 109 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") |
110 interrupts = Param.ArmInterrupts( 111 ArmInterrupts(), "Interrupt Controller") |
112 elif buildEnv['TARGET_ISA'] == 'power': 113 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 114 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 115 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") |
116 interrupts = Param.PowerInterrupts( 117 PowerInterrupts(), "Interrupt Controller") |
118 else: 119 print "Don't know what TLB to use for ISA %s" % \ 120 buildEnv['TARGET_ISA'] 121 sys.exit(1) 122 123 max_insts_all_threads = Param.Counter(0, 124 "terminate when all threads have reached this inst count") 125 max_insts_any_thread = Param.Counter(0, --- 8 unchanged lines hidden (view full) --- 134 defer_registration = Param.Bool(False, 135 "defer registration with system (for sampling)") 136 137 clock = Param.Clock('1t', "clock speed") 138 phase = Param.Latency('0ns', "clock phase") 139 140 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 141 |
142 _cached_ports = [] |
143 if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: |
144 _cached_ports = ["itb.walker.port", "dtb.walker.port"] |
145 146 _uncached_ports = [] |
147 if buildEnv['TARGET_ISA'] == 'x86': |
148 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 149 150 def connectCachedPorts(self, bus): 151 for p in self._cached_ports: 152 exec('self.%s = bus.port' % p) 153 154 def connectUncachedPorts(self, bus): 155 for p in self._uncached_ports: 156 exec('self.%s = bus.port' % p) 157 158 def connectAllPorts(self, cached_bus, uncached_bus = None): 159 self.connectCachedPorts(cached_bus) 160 if not uncached_bus: 161 uncached_bus = cached_bus 162 self.connectUncachedPorts(uncached_bus) 163 164 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): |
165 assert(len(self._cached_ports) < 7) |
166 self.icache = ic 167 self.dcache = dc 168 self.icache_port = ic.cpu_side 169 self.dcache_port = dc.cpu_side 170 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 171 if buildEnv['FULL_SYSTEM']: |
172 if buildEnv['TARGET_ISA'] == 'x86': 173 self.itb_walker_cache = iwc 174 self.dtb_walker_cache = dwc 175 self.itb.walker.port = iwc.cpu_side 176 self.dtb.walker.port = dwc.cpu_side 177 self._cached_ports += ["itb_walker_cache.mem_side", \ 178 "dtb_walker_cache.mem_side"] 179 elif buildEnv['TARGET_ISA'] == 'arm': 180 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] |
181 182 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 183 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 184 self.toL2Bus = Bus() 185 self.connectCachedPorts(self.toL2Bus) 186 self.l2cache = l2c 187 self.l2cache.cpu_side = self.toL2Bus.port 188 self._cached_ports = ['l2cache.mem_side'] |