1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 138 unchanged lines hidden (view full) --- 147 defer_registration = Param.Bool(False, 148 "defer registration with system (for sampling)") 149 150 clock = Param.Clock('1t', "clock speed") 151 phase = Param.Latency('0ns', "clock phase") 152 153 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 154 |
155 icache_port = Port("Instruction Port") 156 dcache_port = Port("Data Port") 157 _cached_ports = ['icache_port', 'dcache_port'] 158 |
159 if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: |
160 _cached_ports += ["itb.walker.port", "dtb.walker.port"] |
161 162 _uncached_ports = [] 163 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: 164 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 165 166 def connectCachedPorts(self, bus): 167 for p in self._cached_ports: 168 exec('self.%s = bus.port' % p) --- 37 unchanged lines hidden --- |