1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 136 unchanged lines hidden (view full) --- 145 defer_registration = Param.Bool(False, 146 "defer registration with system (for sampling)") 147 148 clock = Param.Clock('1t', "clock speed") 149 phase = Param.Latency('0ns', "clock phase") 150 151 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 152 |
153 _cached_ports = [] 154 if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: 155 _cached_ports = ["itb.walker.port", "dtb.walker.port"] 156 157 _uncached_ports = [] |
158 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: |
159 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] |
160 |
161 def connectCachedPorts(self, bus): 162 for p in self._cached_ports: 163 exec('self.%s = bus.port' % p) |
164 |
165 def connectUncachedPorts(self, bus): 166 for p in self._uncached_ports: 167 exec('self.%s = bus.port' % p) |
168 |
169 def connectAllPorts(self, cached_bus, uncached_bus = None): 170 self.connectCachedPorts(cached_bus) 171 if not uncached_bus: 172 uncached_bus = cached_bus 173 self.connectUncachedPorts(uncached_bus) 174 |
175 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): |
176 assert(len(self._cached_ports) < 7) |
177 self.icache = ic 178 self.dcache = dc 179 self.icache_port = ic.cpu_side 180 self.dcache_port = dc.cpu_side |
181 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] |
182 if buildEnv['FULL_SYSTEM']: 183 if buildEnv['TARGET_ISA'] == 'x86': 184 self.itb_walker_cache = iwc 185 self.dtb_walker_cache = dwc 186 self.itb.walker.port = iwc.cpu_side 187 self.dtb.walker.port = dwc.cpu_side |
188 self._cached_ports += ["itb_walker_cache.mem_side", \ 189 "dtb_walker_cache.mem_side"] |
190 elif buildEnv['TARGET_ISA'] == 'arm': |
191 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] |
192 193 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 194 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 195 self.toL2Bus = Bus() |
196 self.connectCachedPorts(self.toL2Bus) |
197 self.l2cache = l2c 198 self.l2cache.cpu_side = self.toL2Bus.port |
199 self._cached_ports = ['l2cache.mem_side'] |
200 201 if buildEnv['TARGET_ISA'] == 'mips': 202 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 203 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 204 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 205 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 206 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 207 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") --- 48 unchanged lines hidden --- |