1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 23 unchanged lines hidden (view full) --- 32from m5 import build_env 33from Bus import Bus 34from InstTracer import InstTracer 35from ExeTracer import ExeTracer 36import sys 37 38default_tracer = ExeTracer() 39 |
40if build_env['TARGET_ISA'] == 'alpha': 41 from AlphaTLB import AlphaDTB, AlphaITB 42elif build_env['TARGET_ISA'] == 'sparc': 43 from SparcTLB import SparcDTB, SparcITB 44elif build_env['TARGET_ISA'] == 'x86': 45 from X86TLB import X86DTB, X86ITB 46elif build_env['TARGET_ISA'] == 'mips': 47 from MipsTLB import MipsDTB, MipsITB |
48 |
49class BaseCPU(SimObject): 50 type = 'BaseCPU' 51 abstract = True 52 53 system = Param.System(Parent.any, "system object") 54 cpu_id = Param.Int("CPU identifier") 55 56 if build_env['FULL_SYSTEM']: 57 do_quiesce = Param.Bool(True, "enable quiesce instructions") 58 do_checkpoint_insts = Param.Bool(True, 59 "enable checkpoint pseudo instructions") 60 do_statistics_insts = Param.Bool(True, 61 "enable statistics pseudo instructions") |
62 else: 63 workload = VectorParam.Process("processes to run") 64 |
65 if build_env['TARGET_ISA'] == 'sparc': 66 dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 67 itb = Param.SparcITB(SparcITB(), "Instruction TLB") 68 elif build_env['TARGET_ISA'] == 'alpha': 69 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 70 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 71 elif build_env['TARGET_ISA'] == 'x86': 72 dtb = Param.X86DTB(X86DTB(), "Data TLB") 73 itb = Param.X86ITB(X86ITB(), "Instruction TLB") 74 elif build_env['TARGET_ISA'] == 'mips': 75 dtb = Param.MipsDTB(MipsDTB(), "Data TLB") 76 itb = Param.MipsITB(MipsITB(), "Instruction TLB") 77 else: 78 print "Don't know what TLB to use for ISA %s" % \ 79 build_env['TARGET_ISA'] 80 sys.exit(1) 81 |
82 max_insts_all_threads = Param.Counter(0, 83 "terminate when all threads have reached this inst count") 84 max_insts_any_thread = Param.Counter(0, 85 "terminate when any thread reaches this inst count") 86 max_loads_all_threads = Param.Counter(0, 87 "terminate when all threads have reached this load count") 88 max_loads_any_thread = Param.Counter(0, 89 "terminate when any thread reaches this load count") --- 33 unchanged lines hidden --- |