1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Nathan Binkert 28 29from m5.SimObject import SimObject 30from m5.params import * 31from m5.proxy import * 32from m5 import build_env 33from Bus import Bus |
34from InstTracer import InstTracer 35from ExeTracer import ExeTracer |
36import sys 37 |
38default_tracer = ExeTracer() 39 |
40if build_env['FULL_SYSTEM']: 41 if build_env['TARGET_ISA'] == 'alpha': 42 from AlphaTLB import AlphaDTB, AlphaITB 43 44 if build_env['TARGET_ISA'] == 'sparc': 45 from SparcTLB import SparcDTB, SparcITB 46 47class BaseCPU(SimObject): --- 34 unchanged lines hidden (view full) --- 82 "interval to print out the progress message") 83 84 defer_registration = Param.Bool(False, 85 "defer registration with system (for sampling)") 86 87 clock = Param.Clock('1t', "clock speed") 88 phase = Param.Latency('0ns', "clock phase") 89 |
90 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 91 |
92 _mem_ports = [] 93 94 def connectMemPorts(self, bus): 95 for p in self._mem_ports: 96 exec('self.%s = bus.port' % p) 97 98 def addPrivateSplitL1Caches(self, ic, dc): 99 assert(len(self._mem_ports) == 2) --- 13 unchanged lines hidden --- |