1# Copyright (c) 2012-2013, 2015-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 231 unchanged lines hidden (view full) --- 240 _uncached_master_ports += ["interrupts[0].int_master"] 241 242 def createInterruptController(self): 243 if buildEnv['TARGET_ISA'] == 'sparc': 244 self.interrupts = [SparcInterrupts() for i in range(self.numThreads)] 245 elif buildEnv['TARGET_ISA'] == 'alpha': 246 self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)] 247 elif buildEnv['TARGET_ISA'] == 'x86': |
248 self.interrupts = [X86LocalApic() for i in range(self.numThreads)] |
249 elif buildEnv['TARGET_ISA'] == 'mips': 250 self.interrupts = [MipsInterrupts() for i in range(self.numThreads)] 251 elif buildEnv['TARGET_ISA'] == 'arm': 252 self.interrupts = [ArmInterrupts() for i in range(self.numThreads)] 253 elif buildEnv['TARGET_ISA'] == 'power': 254 self.interrupts = [PowerInterrupts() for i in range(self.numThreads)] 255 elif buildEnv['TARGET_ISA'] == 'riscv': 256 self.interrupts = \ --- 114 unchanged lines hidden --- |