1# Copyright (c) 2012-2013, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 33 unchanged lines hidden (view full) --- 42# Andreas Hansson 43 44import sys 45 46from m5.defines import buildEnv 47from m5.params import * 48from m5.proxy import * 49 |
50from XBar import L2XBar |
51from InstTracer import InstTracer 52from CPUTracers import ExeTracer 53from MemObject import MemObject 54from ClockDomain import * 55 56default_tracer = ExeTracer() 57 58if buildEnv['TARGET_ISA'] == 'alpha': --- 221 unchanged lines hidden (view full) --- 280 # Checker doesn't need its own tlb caches because it does 281 # functional accesses only 282 if self.checker != NULL: 283 self._cached_ports += ["checker.itb.walker.port", \ 284 "checker.dtb.walker.port"] 285 286 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 287 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) |
288 self.toL2Bus = L2XBar() |
289 self.connectCachedPorts(self.toL2Bus) 290 self.l2cache = l2c 291 self.toL2Bus.master = self.l2cache.cpu_side 292 self._cached_ports = ['l2cache.mem_side'] 293 294 def createThreads(self): 295 self.isa = [ isa_class() for i in xrange(self.numThreads) ] 296 if self.checker != NULL: 297 self.checker.createThreads() 298 299 def addCheckerCpu(self): 300 pass |