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< # Override the default bus clock of 1 GHz and uses the CPU
< # clock for the L1-to-L2 bus, and also set a width of 32 bytes
< # (256-bits), which is four times that of the default bus.
< self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
---
> # Set a width of 32 bytes (256-bits), which is four times that
> # of the default bus. The clock of the CPU is inherited by
> # default.
> self.toL2Bus = CoherentBus(width = 32)