239c239,242
< self.toL2Bus = CoherentBus()
---
> # Override the default bus clock of 1 GHz and uses the CPU
> # clock for the L1-to-L2 bus, and also set a width of 32 bytes
> # (256-bits), which is four times that of the default bus.
> self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
< self.toL2Bus = CoherentBus()
---
> # Override the default bus clock of 1 GHz and uses the CPU
> # clock for the L1-to-L2 bus, and also set a width of 32 bytes
> # (256-bits), which is four times that of the default bus.
> self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)