143,144c143
< if buildEnv['TARGET_ISA'] == 'x86' or \
< (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']):
---
> if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
172,181c171,179
< if buildEnv['FULL_SYSTEM']:
< if buildEnv['TARGET_ISA'] == 'x86':
< self.itb_walker_cache = iwc
< self.dtb_walker_cache = dwc
< self.itb.walker.port = iwc.cpu_side
< self.dtb.walker.port = dwc.cpu_side
< self._cached_ports += ["itb_walker_cache.mem_side", \
< "dtb_walker_cache.mem_side"]
< elif buildEnv['TARGET_ISA'] == 'arm':
< self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
---
> if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc:
> self.itb_walker_cache = iwc
> self.dtb_walker_cache = dwc
> self.itb.walker.port = iwc.cpu_side
> self.dtb.walker.port = dwc.cpu_side
> self._cached_ports += ["itb_walker_cache.mem_side", \
> "dtb_walker_cache.mem_side"]
> elif buildEnv['TARGET_ISA'] == 'arm':
> self._cached_ports += ["itb.walker.port", "dtb.walker.port"]