46,47c46
< if buildEnv['FULL_SYSTEM']:
< from AlphaInterrupts import AlphaInterrupts
---
> from AlphaInterrupts import AlphaInterrupts
50,51c49
< if buildEnv['FULL_SYSTEM']:
< from SparcInterrupts import SparcInterrupts
---
> from SparcInterrupts import SparcInterrupts
54,55c52
< if buildEnv['FULL_SYSTEM']:
< from X86LocalApic import X86LocalApic
---
> from X86LocalApic import X86LocalApic
58,59c55
< if buildEnv['FULL_SYSTEM']:
< from MipsInterrupts import MipsInterrupts
---
> from MipsInterrupts import MipsInterrupts
62,63c58
< if buildEnv['FULL_SYSTEM']:
< from ArmInterrupts import ArmInterrupts
---
> from ArmInterrupts import ArmInterrupts
66,67c61
< if buildEnv['FULL_SYSTEM']:
< from PowerInterrupts import PowerInterrupts
---
> from PowerInterrupts import PowerInterrupts
96,97c90
< if buildEnv['FULL_SYSTEM']:
< interrupts = Param.SparcInterrupts(
---
> interrupts = Param.SparcInterrupts(
102,103c95
< if buildEnv['FULL_SYSTEM']:
< interrupts = Param.AlphaInterrupts(
---
> interrupts = Param.AlphaInterrupts(
108,111c100,101
< if buildEnv['FULL_SYSTEM']:
< _localApic = X86LocalApic(pio_addr=0x2000000000000000)
< interrupts = \
< Param.X86LocalApic(_localApic, "Interrupt Controller")
---
> _localApic = X86LocalApic(pio_addr=0x2000000000000000)
> interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
115,117c105,106
< if buildEnv['FULL_SYSTEM']:
< interrupts = Param.MipsInterrupts(
< MipsInterrupts(), "Interrupt Controller")
---
> interrupts = Param.MipsInterrupts(
> MipsInterrupts(), "Interrupt Controller")
121,123c110,111
< if buildEnv['FULL_SYSTEM']:
< interrupts = Param.ArmInterrupts(
< ArmInterrupts(), "Interrupt Controller")
---
> interrupts = Param.ArmInterrupts(
> ArmInterrupts(), "Interrupt Controller")
128,130c116,117
< if buildEnv['FULL_SYSTEM']:
< interrupts = Param.PowerInterrupts(
< PowerInterrupts(), "Interrupt Controller")
---
> interrupts = Param.PowerInterrupts(
> PowerInterrupts(), "Interrupt Controller")
155,158c142
< icache_port = Port("Instruction Port")
< dcache_port = Port("Data Port")
< _cached_ports = ['icache_port', 'dcache_port']
<
---
> _cached_ports = []
160c144
< _cached_ports += ["itb.walker.port", "dtb.walker.port"]
---
> _cached_ports = ["itb.walker.port", "dtb.walker.port"]
163c147
< if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
---
> if buildEnv['TARGET_ISA'] == 'x86':
180a165
> assert(len(self._cached_ports) < 7)
187,201c172,180
< if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
< if iwc and dwc:
< self.itb_walker_cache = iwc
< self.dtb_walker_cache = dwc
< self.itb.walker.port = iwc.cpu_side
< self.dtb.walker.port = dwc.cpu_side
< self._cached_ports += ["itb_walker_cache.mem_side", \
< "dtb_walker_cache.mem_side"]
< else:
< self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
< # Checker doesn't need its own tlb caches because it does
< # functional accesses only
< if buildEnv['USE_CHECKER']:
< self._cached_ports += ["checker.itb.walker.port", \
< "checker.dtb.walker.port"]
---
> if buildEnv['TARGET_ISA'] == 'x86':
> self.itb_walker_cache = iwc
> self.dtb_walker_cache = dwc
> self.itb.walker.port = iwc.cpu_side
> self.dtb.walker.port = dwc.cpu_side
> self._cached_ports += ["itb_walker_cache.mem_side", \
> "dtb_walker_cache.mem_side"]
> elif buildEnv['TARGET_ISA'] == 'arm':
> self._cached_ports += ["itb.walker.port", "dtb.walker.port"]