153c153,157
< _mem_ports = []
---
> _cached_ports = []
> if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
> _cached_ports = ["itb.walker.port", "dtb.walker.port"]
>
> _uncached_ports = []
155,158c159
< _mem_ports = ["itb.walker.port",
< "dtb.walker.port",
< "interrupts.pio",
< "interrupts.int_port"]
---
> _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
160,162c161,163
< if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']:
< _mem_ports = ["itb.walker.port",
< "dtb.walker.port"]
---
> def connectCachedPorts(self, bus):
> for p in self._cached_ports:
> exec('self.%s = bus.port' % p)
164,167c165,167
< def connectMemPorts(self, bus):
< for p in self._mem_ports:
< if p != 'physmem_port':
< exec('self.%s = bus.port' % p)
---
> def connectUncachedPorts(self, bus):
> for p in self._uncached_ports:
> exec('self.%s = bus.port' % p)
168a169,174
> def connectAllPorts(self, cached_bus, uncached_bus = None):
> self.connectCachedPorts(cached_bus)
> if not uncached_bus:
> uncached_bus = cached_bus
> self.connectUncachedPorts(uncached_bus)
>
170c176
< assert(len(self._mem_ports) < 8)
---
> assert(len(self._cached_ports) < 7)
175c181
< self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
---
> self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
182,184c188,189
< self._mem_ports += ["itb_walker_cache.mem_side", \
< "dtb_walker_cache.mem_side"]
< self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
---
> self._cached_ports += ["itb_walker_cache.mem_side", \
> "dtb_walker_cache.mem_side"]
186c191
< self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
---
> self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
191c196
< self.connectMemPorts(self.toL2Bus)
---
> self.connectCachedPorts(self.toL2Bus)
194c199
< self._mem_ports = ['l2cache.mem_side']
---
> self._cached_ports = ['l2cache.mem_side']