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< def addPrivateSplitL1Caches(self, ic, dc):
---
> def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
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< if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
< self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
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> self.itb_walker_cache = iwc
> self.dtb_walker_cache = dwc
> self.itb.walker.port = iwc.cpu_side
> self.dtb.walker.port = dwc.cpu_side
> self._mem_ports += ["itb_walker_cache.mem_side", \
> "dtb_walker_cache.mem_side"]
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> elif buildEnv['TARGET_ISA'] == 'arm':
> self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
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< def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
< self.addPrivateSplitL1Caches(ic, dc)
---
> def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
> self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)