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< UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
160a160,163
> if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']:
> _mem_ports = ["itb.walker.port",
> "dtb.walker.port"]
>
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< if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
< self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
---
> if buildEnv['FULL_SYSTEM']:
> if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
> self._mem_ports += ["itb.walker.port", "dtb.walker.port"]