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< # Copyright (c) 2012-2013 ARM Limited
---
> # Copyright (c) 2012-2013, 2015 ARM Limited
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< if buildEnv['TARGET_ISA'] in ['arm']:
< _cached_ports += ["istage2_mmu.stage2_tlb.walker.port",
< "dstage2_mmu.stage2_tlb.walker.port"]
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< if buildEnv['TARGET_ISA'] in ['arm']:
< self.itb_walker_cache_bus = CoherentXBar()
< self.dtb_walker_cache_bus = CoherentXBar()
< self.itb_walker_cache_bus.master = iwc.cpu_side
< self.dtb_walker_cache_bus.master = dwc.cpu_side
< self.itb.walker.port = self.itb_walker_cache_bus.slave
< self.dtb.walker.port = self.dtb_walker_cache_bus.slave
< self.istage2_mmu.stage2_tlb.walker.port = self.itb_walker_cache_bus.slave
< self.dstage2_mmu.stage2_tlb.walker.port = self.dtb_walker_cache_bus.slave
< else:
< self.itb.walker.port = iwc.cpu_side
< self.dtb.walker.port = dwc.cpu_side
---
> self.itb.walker.port = iwc.cpu_side
> self.dtb.walker.port = dwc.cpu_side
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< if buildEnv['TARGET_ISA'] in ['arm']:
< self._cached_ports += ["istage2_mmu.stage2_tlb.walker.port", \
< "dstage2_mmu.stage2_tlb.walker.port"]
<
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< if buildEnv['TARGET_ISA'] in ['arm']:
< self._cached_ports += ["checker.istage2_mmu.stage2_tlb.walker.port", \
< "checker.dstage2_mmu.stage2_tlb.walker.port"]