1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58 from AlphaTLB import AlphaDTB, AlphaITB
59 from AlphaInterrupts import AlphaInterrupts
60elif buildEnv['TARGET_ISA'] == 'sparc':
61 from SparcTLB import SparcTLB
62 from SparcInterrupts import SparcInterrupts
63elif buildEnv['TARGET_ISA'] == 'x86':
64 from X86TLB import X86TLB
65 from X86LocalApic import X86LocalApic
66elif buildEnv['TARGET_ISA'] == 'mips':
67 from MipsTLB import MipsTLB
68 from MipsInterrupts import MipsInterrupts
69elif buildEnv['TARGET_ISA'] == 'arm':
70 from ArmTLB import ArmTLB
71 from ArmInterrupts import ArmInterrupts
72elif buildEnv['TARGET_ISA'] == 'power':
73 from PowerTLB import PowerTLB
74 from PowerInterrupts import PowerInterrupts
75
76class BaseCPU(MemObject):
77 type = 'BaseCPU'
78 abstract = True
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58 from AlphaTLB import AlphaDTB, AlphaITB
59 from AlphaInterrupts import AlphaInterrupts
60elif buildEnv['TARGET_ISA'] == 'sparc':
61 from SparcTLB import SparcTLB
62 from SparcInterrupts import SparcInterrupts
63elif buildEnv['TARGET_ISA'] == 'x86':
64 from X86TLB import X86TLB
65 from X86LocalApic import X86LocalApic
66elif buildEnv['TARGET_ISA'] == 'mips':
67 from MipsTLB import MipsTLB
68 from MipsInterrupts import MipsInterrupts
69elif buildEnv['TARGET_ISA'] == 'arm':
70 from ArmTLB import ArmTLB
71 from ArmInterrupts import ArmInterrupts
72elif buildEnv['TARGET_ISA'] == 'power':
73 from PowerTLB import PowerTLB
74 from PowerInterrupts import PowerInterrupts
75
76class BaseCPU(MemObject):
77 type = 'BaseCPU'
78 abstract = True
|
86 def export_methods(cls, code):
87 code('''
88 void switchOut();
89 void takeOverFrom(BaseCPU *cpu);
90''')
91
92 def takeOverFrom(self, old_cpu):
93 self._ccObject.takeOverFrom(old_cpu._ccObject)
94
95
96 system = Param.System(Parent.any, "system object")
97 cpu_id = Param.Int(-1, "CPU identifier")
98 numThreads = Param.Unsigned(1, "number of HW thread contexts")
99
100 function_trace = Param.Bool(False, "Enable function trace")
101 function_trace_start = Param.Tick(0, "Tick to start function trace")
102
103 checker = Param.BaseCPU(NULL, "checker CPU")
104
105 do_checkpoint_insts = Param.Bool(True,
106 "enable checkpoint pseudo instructions")
107 do_statistics_insts = Param.Bool(True,
108 "enable statistics pseudo instructions")
109
110 profile = Param.Latency('0ns', "trace the kernel stack")
111 do_quiesce = Param.Bool(True, "enable quiesce instructions")
112
113 workload = VectorParam.Process([], "processes to run")
114
115 if buildEnv['TARGET_ISA'] == 'sparc':
116 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
117 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
118 interrupts = Param.SparcInterrupts(
119 NULL, "Interrupt Controller")
120 elif buildEnv['TARGET_ISA'] == 'alpha':
121 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
122 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
123 interrupts = Param.AlphaInterrupts(
124 NULL, "Interrupt Controller")
125 elif buildEnv['TARGET_ISA'] == 'x86':
126 dtb = Param.X86TLB(X86TLB(), "Data TLB")
127 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
128 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
129 elif buildEnv['TARGET_ISA'] == 'mips':
130 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
131 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
132 interrupts = Param.MipsInterrupts(
133 NULL, "Interrupt Controller")
134 elif buildEnv['TARGET_ISA'] == 'arm':
135 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
136 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
137 interrupts = Param.ArmInterrupts(
138 NULL, "Interrupt Controller")
139 elif buildEnv['TARGET_ISA'] == 'power':
140 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
141 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
142 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
143 interrupts = Param.PowerInterrupts(
144 NULL, "Interrupt Controller")
145 else:
146 print "Don't know what TLB to use for ISA %s" % \
147 buildEnv['TARGET_ISA']
148 sys.exit(1)
149
150 max_insts_all_threads = Param.Counter(0,
151 "terminate when all threads have reached this inst count")
152 max_insts_any_thread = Param.Counter(0,
153 "terminate when any thread reaches this inst count")
154 max_loads_all_threads = Param.Counter(0,
155 "terminate when all threads have reached this load count")
156 max_loads_any_thread = Param.Counter(0,
157 "terminate when any thread reaches this load count")
158 progress_interval = Param.Frequency('0Hz',
159 "frequency to print out the progress message")
160
161 defer_registration = Param.Bool(False,
162 "defer registration with system (for sampling)")
163
164 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
165
166 icache_port = MasterPort("Instruction Port")
167 dcache_port = MasterPort("Data Port")
168 _cached_ports = ['icache_port', 'dcache_port']
169
170 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
171 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
172
173 _uncached_slave_ports = []
174 _uncached_master_ports = []
175 if buildEnv['TARGET_ISA'] == 'x86':
176 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
177 _uncached_master_ports += ["interrupts.int_master"]
178
179 def createInterruptController(self):
180 if buildEnv['TARGET_ISA'] == 'sparc':
181 self.interrupts = SparcInterrupts()
182 elif buildEnv['TARGET_ISA'] == 'alpha':
183 self.interrupts = AlphaInterrupts()
184 elif buildEnv['TARGET_ISA'] == 'x86':
185 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
186 self.interrupts = _localApic
187 elif buildEnv['TARGET_ISA'] == 'mips':
188 self.interrupts = MipsInterrupts()
189 elif buildEnv['TARGET_ISA'] == 'arm':
190 self.interrupts = ArmInterrupts()
191 elif buildEnv['TARGET_ISA'] == 'power':
192 self.interrupts = PowerInterrupts()
193 else:
194 print "Don't know what Interrupt Controller to use for ISA %s" % \
195 buildEnv['TARGET_ISA']
196 sys.exit(1)
197
198 def connectCachedPorts(self, bus):
199 for p in self._cached_ports:
200 exec('self.%s = bus.slave' % p)
201
202 def connectUncachedPorts(self, bus):
203 for p in self._uncached_slave_ports:
204 exec('self.%s = bus.master' % p)
205 for p in self._uncached_master_ports:
206 exec('self.%s = bus.slave' % p)
207
208 def connectAllPorts(self, cached_bus, uncached_bus = None):
209 self.connectCachedPorts(cached_bus)
210 if not uncached_bus:
211 uncached_bus = cached_bus
212 self.connectUncachedPorts(uncached_bus)
213
214 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
215 self.icache = ic
216 self.dcache = dc
217 self.icache_port = ic.cpu_side
218 self.dcache_port = dc.cpu_side
219 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
220 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
221 if iwc and dwc:
222 self.itb_walker_cache = iwc
223 self.dtb_walker_cache = dwc
224 self.itb.walker.port = iwc.cpu_side
225 self.dtb.walker.port = dwc.cpu_side
226 self._cached_ports += ["itb_walker_cache.mem_side", \
227 "dtb_walker_cache.mem_side"]
228 else:
229 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
230
231 # Checker doesn't need its own tlb caches because it does
232 # functional accesses only
233 if self.checker != NULL:
234 self._cached_ports += ["checker.itb.walker.port", \
235 "checker.dtb.walker.port"]
236
237 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
238 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
239 # Override the default bus clock of 1 GHz and uses the CPU
240 # clock for the L1-to-L2 bus, and also set a width of 32 bytes
241 # (256-bits), which is four times that of the default bus.
242 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
243 self.connectCachedPorts(self.toL2Bus)
244 self.l2cache = l2c
245 self.toL2Bus.master = self.l2cache.cpu_side
246 self._cached_ports = ['l2cache.mem_side']
247
248 def addCheckerCpu(self):
249 pass
| 82 def export_methods(cls, code):
83 code('''
84 void switchOut();
85 void takeOverFrom(BaseCPU *cpu);
86''')
87
88 def takeOverFrom(self, old_cpu):
89 self._ccObject.takeOverFrom(old_cpu._ccObject)
90
91
92 system = Param.System(Parent.any, "system object")
93 cpu_id = Param.Int(-1, "CPU identifier")
94 numThreads = Param.Unsigned(1, "number of HW thread contexts")
95
96 function_trace = Param.Bool(False, "Enable function trace")
97 function_trace_start = Param.Tick(0, "Tick to start function trace")
98
99 checker = Param.BaseCPU(NULL, "checker CPU")
100
101 do_checkpoint_insts = Param.Bool(True,
102 "enable checkpoint pseudo instructions")
103 do_statistics_insts = Param.Bool(True,
104 "enable statistics pseudo instructions")
105
106 profile = Param.Latency('0ns', "trace the kernel stack")
107 do_quiesce = Param.Bool(True, "enable quiesce instructions")
108
109 workload = VectorParam.Process([], "processes to run")
110
111 if buildEnv['TARGET_ISA'] == 'sparc':
112 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
113 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
114 interrupts = Param.SparcInterrupts(
115 NULL, "Interrupt Controller")
116 elif buildEnv['TARGET_ISA'] == 'alpha':
117 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
118 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
119 interrupts = Param.AlphaInterrupts(
120 NULL, "Interrupt Controller")
121 elif buildEnv['TARGET_ISA'] == 'x86':
122 dtb = Param.X86TLB(X86TLB(), "Data TLB")
123 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
124 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
125 elif buildEnv['TARGET_ISA'] == 'mips':
126 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
127 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
128 interrupts = Param.MipsInterrupts(
129 NULL, "Interrupt Controller")
130 elif buildEnv['TARGET_ISA'] == 'arm':
131 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
132 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
133 interrupts = Param.ArmInterrupts(
134 NULL, "Interrupt Controller")
135 elif buildEnv['TARGET_ISA'] == 'power':
136 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
137 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
138 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
139 interrupts = Param.PowerInterrupts(
140 NULL, "Interrupt Controller")
141 else:
142 print "Don't know what TLB to use for ISA %s" % \
143 buildEnv['TARGET_ISA']
144 sys.exit(1)
145
146 max_insts_all_threads = Param.Counter(0,
147 "terminate when all threads have reached this inst count")
148 max_insts_any_thread = Param.Counter(0,
149 "terminate when any thread reaches this inst count")
150 max_loads_all_threads = Param.Counter(0,
151 "terminate when all threads have reached this load count")
152 max_loads_any_thread = Param.Counter(0,
153 "terminate when any thread reaches this load count")
154 progress_interval = Param.Frequency('0Hz',
155 "frequency to print out the progress message")
156
157 defer_registration = Param.Bool(False,
158 "defer registration with system (for sampling)")
159
160 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
161
162 icache_port = MasterPort("Instruction Port")
163 dcache_port = MasterPort("Data Port")
164 _cached_ports = ['icache_port', 'dcache_port']
165
166 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
167 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
168
169 _uncached_slave_ports = []
170 _uncached_master_ports = []
171 if buildEnv['TARGET_ISA'] == 'x86':
172 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
173 _uncached_master_ports += ["interrupts.int_master"]
174
175 def createInterruptController(self):
176 if buildEnv['TARGET_ISA'] == 'sparc':
177 self.interrupts = SparcInterrupts()
178 elif buildEnv['TARGET_ISA'] == 'alpha':
179 self.interrupts = AlphaInterrupts()
180 elif buildEnv['TARGET_ISA'] == 'x86':
181 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
182 self.interrupts = _localApic
183 elif buildEnv['TARGET_ISA'] == 'mips':
184 self.interrupts = MipsInterrupts()
185 elif buildEnv['TARGET_ISA'] == 'arm':
186 self.interrupts = ArmInterrupts()
187 elif buildEnv['TARGET_ISA'] == 'power':
188 self.interrupts = PowerInterrupts()
189 else:
190 print "Don't know what Interrupt Controller to use for ISA %s" % \
191 buildEnv['TARGET_ISA']
192 sys.exit(1)
193
194 def connectCachedPorts(self, bus):
195 for p in self._cached_ports:
196 exec('self.%s = bus.slave' % p)
197
198 def connectUncachedPorts(self, bus):
199 for p in self._uncached_slave_ports:
200 exec('self.%s = bus.master' % p)
201 for p in self._uncached_master_ports:
202 exec('self.%s = bus.slave' % p)
203
204 def connectAllPorts(self, cached_bus, uncached_bus = None):
205 self.connectCachedPorts(cached_bus)
206 if not uncached_bus:
207 uncached_bus = cached_bus
208 self.connectUncachedPorts(uncached_bus)
209
210 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
211 self.icache = ic
212 self.dcache = dc
213 self.icache_port = ic.cpu_side
214 self.dcache_port = dc.cpu_side
215 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
216 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
217 if iwc and dwc:
218 self.itb_walker_cache = iwc
219 self.dtb_walker_cache = dwc
220 self.itb.walker.port = iwc.cpu_side
221 self.dtb.walker.port = dwc.cpu_side
222 self._cached_ports += ["itb_walker_cache.mem_side", \
223 "dtb_walker_cache.mem_side"]
224 else:
225 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
226
227 # Checker doesn't need its own tlb caches because it does
228 # functional accesses only
229 if self.checker != NULL:
230 self._cached_ports += ["checker.itb.walker.port", \
231 "checker.dtb.walker.port"]
232
233 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
234 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
235 # Override the default bus clock of 1 GHz and uses the CPU
236 # clock for the L1-to-L2 bus, and also set a width of 32 bytes
237 # (256-bits), which is four times that of the default bus.
238 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
239 self.connectCachedPorts(self.toL2Bus)
240 self.l2cache = l2c
241 self.toL2Bus.master = self.l2cache.cpu_side
242 self._cached_ports = ['l2cache.mem_side']
243
244 def addCheckerCpu(self):
245 pass
|