1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58 from AlphaTLB import AlphaDTB, AlphaITB
59 from AlphaInterrupts import AlphaInterrupts
60elif buildEnv['TARGET_ISA'] == 'sparc':
61 from SparcTLB import SparcTLB
62 from SparcInterrupts import SparcInterrupts
63elif buildEnv['TARGET_ISA'] == 'x86':
64 from X86TLB import X86TLB
65 from X86LocalApic import X86LocalApic
66elif buildEnv['TARGET_ISA'] == 'mips':
67 from MipsTLB import MipsTLB
68 from MipsInterrupts import MipsInterrupts
69elif buildEnv['TARGET_ISA'] == 'arm':
70 from ArmTLB import ArmTLB
71 from ArmInterrupts import ArmInterrupts
72elif buildEnv['TARGET_ISA'] == 'power':
73 from PowerTLB import PowerTLB
74 from PowerInterrupts import PowerInterrupts
75
76class BaseCPU(MemObject):
77 type = 'BaseCPU'
78 abstract = True
79
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58 from AlphaTLB import AlphaDTB, AlphaITB
59 from AlphaInterrupts import AlphaInterrupts
60elif buildEnv['TARGET_ISA'] == 'sparc':
61 from SparcTLB import SparcTLB
62 from SparcInterrupts import SparcInterrupts
63elif buildEnv['TARGET_ISA'] == 'x86':
64 from X86TLB import X86TLB
65 from X86LocalApic import X86LocalApic
66elif buildEnv['TARGET_ISA'] == 'mips':
67 from MipsTLB import MipsTLB
68 from MipsInterrupts import MipsInterrupts
69elif buildEnv['TARGET_ISA'] == 'arm':
70 from ArmTLB import ArmTLB
71 from ArmInterrupts import ArmInterrupts
72elif buildEnv['TARGET_ISA'] == 'power':
73 from PowerTLB import PowerTLB
74 from PowerInterrupts import PowerInterrupts
75
76class BaseCPU(MemObject):
77 type = 'BaseCPU'
78 abstract = True
79
|
80 system = Param.System(Parent.any, "system object")
81 cpu_id = Param.Int(-1, "CPU identifier")
82 numThreads = Param.Unsigned(1, "number of HW thread contexts")
83
84 function_trace = Param.Bool(False, "Enable function trace")
85 function_trace_start = Param.Tick(0, "Tick to start function trace")
86
87 checker = Param.BaseCPU(NULL, "checker CPU")
88
89 do_checkpoint_insts = Param.Bool(True,
90 "enable checkpoint pseudo instructions")
91 do_statistics_insts = Param.Bool(True,
92 "enable statistics pseudo instructions")
93
94 profile = Param.Latency('0ns', "trace the kernel stack")
95 do_quiesce = Param.Bool(True, "enable quiesce instructions")
96
97 workload = VectorParam.Process([], "processes to run")
98
99 if buildEnv['TARGET_ISA'] == 'sparc':
100 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
101 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
102 interrupts = Param.SparcInterrupts(
103 NULL, "Interrupt Controller")
104 elif buildEnv['TARGET_ISA'] == 'alpha':
105 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
106 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
107 interrupts = Param.AlphaInterrupts(
108 NULL, "Interrupt Controller")
109 elif buildEnv['TARGET_ISA'] == 'x86':
110 dtb = Param.X86TLB(X86TLB(), "Data TLB")
111 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
112 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
113 elif buildEnv['TARGET_ISA'] == 'mips':
114 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
115 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
116 interrupts = Param.MipsInterrupts(
117 NULL, "Interrupt Controller")
118 elif buildEnv['TARGET_ISA'] == 'arm':
119 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
120 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
121 interrupts = Param.ArmInterrupts(
122 NULL, "Interrupt Controller")
123 elif buildEnv['TARGET_ISA'] == 'power':
124 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
125 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
126 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
127 interrupts = Param.PowerInterrupts(
128 NULL, "Interrupt Controller")
129 else:
130 print "Don't know what TLB to use for ISA %s" % \
131 buildEnv['TARGET_ISA']
132 sys.exit(1)
133
134 max_insts_all_threads = Param.Counter(0,
135 "terminate when all threads have reached this inst count")
136 max_insts_any_thread = Param.Counter(0,
137 "terminate when any thread reaches this inst count")
138 max_loads_all_threads = Param.Counter(0,
139 "terminate when all threads have reached this load count")
140 max_loads_any_thread = Param.Counter(0,
141 "terminate when any thread reaches this load count")
142 progress_interval = Param.Frequency('0Hz',
143 "frequency to print out the progress message")
144
145 defer_registration = Param.Bool(False,
146 "defer registration with system (for sampling)")
147
148 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
149
150 icache_port = MasterPort("Instruction Port")
151 dcache_port = MasterPort("Data Port")
152 _cached_ports = ['icache_port', 'dcache_port']
153
154 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
155 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
156
157 _uncached_slave_ports = []
158 _uncached_master_ports = []
159 if buildEnv['TARGET_ISA'] == 'x86':
160 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
161 _uncached_master_ports += ["interrupts.int_master"]
162
163 def createInterruptController(self):
164 if buildEnv['TARGET_ISA'] == 'sparc':
165 self.interrupts = SparcInterrupts()
166 elif buildEnv['TARGET_ISA'] == 'alpha':
167 self.interrupts = AlphaInterrupts()
168 elif buildEnv['TARGET_ISA'] == 'x86':
169 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
170 self.interrupts = _localApic
171 elif buildEnv['TARGET_ISA'] == 'mips':
172 self.interrupts = MipsInterrupts()
173 elif buildEnv['TARGET_ISA'] == 'arm':
174 self.interrupts = ArmInterrupts()
175 elif buildEnv['TARGET_ISA'] == 'power':
176 self.interrupts = PowerInterrupts()
177 else:
178 print "Don't know what Interrupt Controller to use for ISA %s" % \
179 buildEnv['TARGET_ISA']
180 sys.exit(1)
181
182 def connectCachedPorts(self, bus):
183 for p in self._cached_ports:
184 exec('self.%s = bus.slave' % p)
185
186 def connectUncachedPorts(self, bus):
187 for p in self._uncached_slave_ports:
188 exec('self.%s = bus.master' % p)
189 for p in self._uncached_master_ports:
190 exec('self.%s = bus.slave' % p)
191
192 def connectAllPorts(self, cached_bus, uncached_bus = None):
193 self.connectCachedPorts(cached_bus)
194 if not uncached_bus:
195 uncached_bus = cached_bus
196 self.connectUncachedPorts(uncached_bus)
197
198 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
199 self.icache = ic
200 self.dcache = dc
201 self.icache_port = ic.cpu_side
202 self.dcache_port = dc.cpu_side
203 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
204 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
205 if iwc and dwc:
206 self.itb_walker_cache = iwc
207 self.dtb_walker_cache = dwc
208 self.itb.walker.port = iwc.cpu_side
209 self.dtb.walker.port = dwc.cpu_side
210 self._cached_ports += ["itb_walker_cache.mem_side", \
211 "dtb_walker_cache.mem_side"]
212 else:
213 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
214
215 # Checker doesn't need its own tlb caches because it does
216 # functional accesses only
217 if self.checker != NULL:
218 self._cached_ports += ["checker.itb.walker.port", \
219 "checker.dtb.walker.port"]
220
221 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
222 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
223 self.toL2Bus = CoherentBus()
224 self.connectCachedPorts(self.toL2Bus)
225 self.l2cache = l2c
226 self.toL2Bus.master = self.l2cache.cpu_side
227 self._cached_ports = ['l2cache.mem_side']
228
229 def addCheckerCpu(self):
230 pass
| 96 system = Param.System(Parent.any, "system object")
97 cpu_id = Param.Int(-1, "CPU identifier")
98 numThreads = Param.Unsigned(1, "number of HW thread contexts")
99
100 function_trace = Param.Bool(False, "Enable function trace")
101 function_trace_start = Param.Tick(0, "Tick to start function trace")
102
103 checker = Param.BaseCPU(NULL, "checker CPU")
104
105 do_checkpoint_insts = Param.Bool(True,
106 "enable checkpoint pseudo instructions")
107 do_statistics_insts = Param.Bool(True,
108 "enable statistics pseudo instructions")
109
110 profile = Param.Latency('0ns', "trace the kernel stack")
111 do_quiesce = Param.Bool(True, "enable quiesce instructions")
112
113 workload = VectorParam.Process([], "processes to run")
114
115 if buildEnv['TARGET_ISA'] == 'sparc':
116 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
117 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
118 interrupts = Param.SparcInterrupts(
119 NULL, "Interrupt Controller")
120 elif buildEnv['TARGET_ISA'] == 'alpha':
121 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
122 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
123 interrupts = Param.AlphaInterrupts(
124 NULL, "Interrupt Controller")
125 elif buildEnv['TARGET_ISA'] == 'x86':
126 dtb = Param.X86TLB(X86TLB(), "Data TLB")
127 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
128 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
129 elif buildEnv['TARGET_ISA'] == 'mips':
130 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
131 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
132 interrupts = Param.MipsInterrupts(
133 NULL, "Interrupt Controller")
134 elif buildEnv['TARGET_ISA'] == 'arm':
135 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
136 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
137 interrupts = Param.ArmInterrupts(
138 NULL, "Interrupt Controller")
139 elif buildEnv['TARGET_ISA'] == 'power':
140 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
141 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
142 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
143 interrupts = Param.PowerInterrupts(
144 NULL, "Interrupt Controller")
145 else:
146 print "Don't know what TLB to use for ISA %s" % \
147 buildEnv['TARGET_ISA']
148 sys.exit(1)
149
150 max_insts_all_threads = Param.Counter(0,
151 "terminate when all threads have reached this inst count")
152 max_insts_any_thread = Param.Counter(0,
153 "terminate when any thread reaches this inst count")
154 max_loads_all_threads = Param.Counter(0,
155 "terminate when all threads have reached this load count")
156 max_loads_any_thread = Param.Counter(0,
157 "terminate when any thread reaches this load count")
158 progress_interval = Param.Frequency('0Hz',
159 "frequency to print out the progress message")
160
161 defer_registration = Param.Bool(False,
162 "defer registration with system (for sampling)")
163
164 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
165
166 icache_port = MasterPort("Instruction Port")
167 dcache_port = MasterPort("Data Port")
168 _cached_ports = ['icache_port', 'dcache_port']
169
170 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
171 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
172
173 _uncached_slave_ports = []
174 _uncached_master_ports = []
175 if buildEnv['TARGET_ISA'] == 'x86':
176 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
177 _uncached_master_ports += ["interrupts.int_master"]
178
179 def createInterruptController(self):
180 if buildEnv['TARGET_ISA'] == 'sparc':
181 self.interrupts = SparcInterrupts()
182 elif buildEnv['TARGET_ISA'] == 'alpha':
183 self.interrupts = AlphaInterrupts()
184 elif buildEnv['TARGET_ISA'] == 'x86':
185 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
186 self.interrupts = _localApic
187 elif buildEnv['TARGET_ISA'] == 'mips':
188 self.interrupts = MipsInterrupts()
189 elif buildEnv['TARGET_ISA'] == 'arm':
190 self.interrupts = ArmInterrupts()
191 elif buildEnv['TARGET_ISA'] == 'power':
192 self.interrupts = PowerInterrupts()
193 else:
194 print "Don't know what Interrupt Controller to use for ISA %s" % \
195 buildEnv['TARGET_ISA']
196 sys.exit(1)
197
198 def connectCachedPorts(self, bus):
199 for p in self._cached_ports:
200 exec('self.%s = bus.slave' % p)
201
202 def connectUncachedPorts(self, bus):
203 for p in self._uncached_slave_ports:
204 exec('self.%s = bus.master' % p)
205 for p in self._uncached_master_ports:
206 exec('self.%s = bus.slave' % p)
207
208 def connectAllPorts(self, cached_bus, uncached_bus = None):
209 self.connectCachedPorts(cached_bus)
210 if not uncached_bus:
211 uncached_bus = cached_bus
212 self.connectUncachedPorts(uncached_bus)
213
214 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
215 self.icache = ic
216 self.dcache = dc
217 self.icache_port = ic.cpu_side
218 self.dcache_port = dc.cpu_side
219 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
220 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
221 if iwc and dwc:
222 self.itb_walker_cache = iwc
223 self.dtb_walker_cache = dwc
224 self.itb.walker.port = iwc.cpu_side
225 self.dtb.walker.port = dwc.cpu_side
226 self._cached_ports += ["itb_walker_cache.mem_side", \
227 "dtb_walker_cache.mem_side"]
228 else:
229 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
230
231 # Checker doesn't need its own tlb caches because it does
232 # functional accesses only
233 if self.checker != NULL:
234 self._cached_ports += ["checker.itb.walker.port", \
235 "checker.dtb.walker.port"]
236
237 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
238 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
239 self.toL2Bus = CoherentBus()
240 self.connectCachedPorts(self.toL2Bus)
241 self.l2cache = l2c
242 self.toL2Bus.master = self.l2cache.cpu_side
243 self._cached_ports = ['l2cache.mem_side']
244
245 def addCheckerCpu(self):
246 pass
|