1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Nathan Binkert
29# Rick Strong
30
31import sys
32
33from m5.defines import buildEnv
34from m5.params import *
35from m5.proxy import *
36
37from Bus import Bus
38from InstTracer import InstTracer
39from ExeTracer import ExeTracer
40from MemObject import MemObject
41
42default_tracer = ExeTracer()
43
44if buildEnv['TARGET_ISA'] == 'alpha':
45 from AlphaTLB import AlphaDTB, AlphaITB
46 from AlphaInterrupts import AlphaInterrupts
47elif buildEnv['TARGET_ISA'] == 'sparc':
48 from SparcTLB import SparcTLB
49 from SparcInterrupts import SparcInterrupts
50elif buildEnv['TARGET_ISA'] == 'x86':
51 from X86TLB import X86TLB
52 from X86LocalApic import X86LocalApic
53elif buildEnv['TARGET_ISA'] == 'mips':
54 from MipsTLB import MipsTLB
55 from MipsInterrupts import MipsInterrupts
56elif buildEnv['TARGET_ISA'] == 'arm':
57 from ArmTLB import ArmTLB
58 from ArmInterrupts import ArmInterrupts
59elif buildEnv['TARGET_ISA'] == 'power':
60 from PowerTLB import PowerTLB
61 from PowerInterrupts import PowerInterrupts
62
63class BaseCPU(MemObject):
64 type = 'BaseCPU'
65 abstract = True
66
67 system = Param.System(Parent.any, "system object")
68 cpu_id = Param.Int(-1, "CPU identifier")
69 numThreads = Param.Unsigned(1, "number of HW thread contexts")
70
71 function_trace = Param.Bool(False, "Enable function trace")
72 function_trace_start = Param.Tick(0, "Cycle to start function trace")
73
74 checker = Param.BaseCPU(NULL, "checker CPU")
75
76 do_checkpoint_insts = Param.Bool(True,
77 "enable checkpoint pseudo instructions")
78 do_statistics_insts = Param.Bool(True,
79 "enable statistics pseudo instructions")
80
81 if buildEnv['FULL_SYSTEM']:
82 profile = Param.Latency('0ns', "trace the kernel stack")
83 do_quiesce = Param.Bool(True, "enable quiesce instructions")
84 else:
85 workload = VectorParam.Process("processes to run")
86
87 if buildEnv['TARGET_ISA'] == 'sparc':
88 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
89 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
90 interrupts = Param.SparcInterrupts(
91 SparcInterrupts(), "Interrupt Controller")
92 elif buildEnv['TARGET_ISA'] == 'alpha':
93 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
94 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
95 interrupts = Param.AlphaInterrupts(
96 AlphaInterrupts(), "Interrupt Controller")
97 elif buildEnv['TARGET_ISA'] == 'x86':
98 dtb = Param.X86TLB(X86TLB(), "Data TLB")
99 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
100 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
101 interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
102 elif buildEnv['TARGET_ISA'] == 'mips':
103 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
104 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
105 interrupts = Param.MipsInterrupts(
106 MipsInterrupts(), "Interrupt Controller")
107 elif buildEnv['TARGET_ISA'] == 'arm':
108 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
109 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
110 interrupts = Param.ArmInterrupts(
111 ArmInterrupts(), "Interrupt Controller")
112 elif buildEnv['TARGET_ISA'] == 'power':
113 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
114 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
115 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
116 interrupts = Param.PowerInterrupts(
117 PowerInterrupts(), "Interrupt Controller")
118 else:
119 print "Don't know what TLB to use for ISA %s" % \
120 buildEnv['TARGET_ISA']
121 sys.exit(1)
122
123 max_insts_all_threads = Param.Counter(0,
124 "terminate when all threads have reached this inst count")
125 max_insts_any_thread = Param.Counter(0,
126 "terminate when any thread reaches this inst count")
127 max_loads_all_threads = Param.Counter(0,
128 "terminate when all threads have reached this load count")
129 max_loads_any_thread = Param.Counter(0,
130 "terminate when any thread reaches this load count")
131 progress_interval = Param.Tick(0,
132 "interval to print out the progress message")
133
134 defer_registration = Param.Bool(False,
135 "defer registration with system (for sampling)")
136
137 clock = Param.Clock('1t', "clock speed")
138 phase = Param.Latency('0ns', "clock phase")
139
140 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
141
142 _cached_ports = []
| 1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Nathan Binkert
29# Rick Strong
30
31import sys
32
33from m5.defines import buildEnv
34from m5.params import *
35from m5.proxy import *
36
37from Bus import Bus
38from InstTracer import InstTracer
39from ExeTracer import ExeTracer
40from MemObject import MemObject
41
42default_tracer = ExeTracer()
43
44if buildEnv['TARGET_ISA'] == 'alpha':
45 from AlphaTLB import AlphaDTB, AlphaITB
46 from AlphaInterrupts import AlphaInterrupts
47elif buildEnv['TARGET_ISA'] == 'sparc':
48 from SparcTLB import SparcTLB
49 from SparcInterrupts import SparcInterrupts
50elif buildEnv['TARGET_ISA'] == 'x86':
51 from X86TLB import X86TLB
52 from X86LocalApic import X86LocalApic
53elif buildEnv['TARGET_ISA'] == 'mips':
54 from MipsTLB import MipsTLB
55 from MipsInterrupts import MipsInterrupts
56elif buildEnv['TARGET_ISA'] == 'arm':
57 from ArmTLB import ArmTLB
58 from ArmInterrupts import ArmInterrupts
59elif buildEnv['TARGET_ISA'] == 'power':
60 from PowerTLB import PowerTLB
61 from PowerInterrupts import PowerInterrupts
62
63class BaseCPU(MemObject):
64 type = 'BaseCPU'
65 abstract = True
66
67 system = Param.System(Parent.any, "system object")
68 cpu_id = Param.Int(-1, "CPU identifier")
69 numThreads = Param.Unsigned(1, "number of HW thread contexts")
70
71 function_trace = Param.Bool(False, "Enable function trace")
72 function_trace_start = Param.Tick(0, "Cycle to start function trace")
73
74 checker = Param.BaseCPU(NULL, "checker CPU")
75
76 do_checkpoint_insts = Param.Bool(True,
77 "enable checkpoint pseudo instructions")
78 do_statistics_insts = Param.Bool(True,
79 "enable statistics pseudo instructions")
80
81 if buildEnv['FULL_SYSTEM']:
82 profile = Param.Latency('0ns', "trace the kernel stack")
83 do_quiesce = Param.Bool(True, "enable quiesce instructions")
84 else:
85 workload = VectorParam.Process("processes to run")
86
87 if buildEnv['TARGET_ISA'] == 'sparc':
88 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
89 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
90 interrupts = Param.SparcInterrupts(
91 SparcInterrupts(), "Interrupt Controller")
92 elif buildEnv['TARGET_ISA'] == 'alpha':
93 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
94 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
95 interrupts = Param.AlphaInterrupts(
96 AlphaInterrupts(), "Interrupt Controller")
97 elif buildEnv['TARGET_ISA'] == 'x86':
98 dtb = Param.X86TLB(X86TLB(), "Data TLB")
99 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
100 _localApic = X86LocalApic(pio_addr=0x2000000000000000)
101 interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
102 elif buildEnv['TARGET_ISA'] == 'mips':
103 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
104 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
105 interrupts = Param.MipsInterrupts(
106 MipsInterrupts(), "Interrupt Controller")
107 elif buildEnv['TARGET_ISA'] == 'arm':
108 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
109 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
110 interrupts = Param.ArmInterrupts(
111 ArmInterrupts(), "Interrupt Controller")
112 elif buildEnv['TARGET_ISA'] == 'power':
113 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
114 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
115 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
116 interrupts = Param.PowerInterrupts(
117 PowerInterrupts(), "Interrupt Controller")
118 else:
119 print "Don't know what TLB to use for ISA %s" % \
120 buildEnv['TARGET_ISA']
121 sys.exit(1)
122
123 max_insts_all_threads = Param.Counter(0,
124 "terminate when all threads have reached this inst count")
125 max_insts_any_thread = Param.Counter(0,
126 "terminate when any thread reaches this inst count")
127 max_loads_all_threads = Param.Counter(0,
128 "terminate when all threads have reached this load count")
129 max_loads_any_thread = Param.Counter(0,
130 "terminate when any thread reaches this load count")
131 progress_interval = Param.Tick(0,
132 "interval to print out the progress message")
133
134 defer_registration = Param.Bool(False,
135 "defer registration with system (for sampling)")
136
137 clock = Param.Clock('1t', "clock speed")
138 phase = Param.Latency('0ns', "clock phase")
139
140 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
141
142 _cached_ports = []
|
145 _cached_ports = ["itb.walker.port", "dtb.walker.port"]
146
147 _uncached_ports = []
148 if buildEnv['TARGET_ISA'] == 'x86':
149 _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
150
151 def connectCachedPorts(self, bus):
152 for p in self._cached_ports:
153 exec('self.%s = bus.port' % p)
154
155 def connectUncachedPorts(self, bus):
156 for p in self._uncached_ports:
157 exec('self.%s = bus.port' % p)
158
159 def connectAllPorts(self, cached_bus, uncached_bus = None):
160 self.connectCachedPorts(cached_bus)
161 if not uncached_bus:
162 uncached_bus = cached_bus
163 self.connectUncachedPorts(uncached_bus)
164
165 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
166 assert(len(self._cached_ports) < 7)
167 self.icache = ic
168 self.dcache = dc
169 self.icache_port = ic.cpu_side
170 self.dcache_port = dc.cpu_side
171 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
| 144 _cached_ports = ["itb.walker.port", "dtb.walker.port"]
145
146 _uncached_ports = []
147 if buildEnv['TARGET_ISA'] == 'x86':
148 _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
149
150 def connectCachedPorts(self, bus):
151 for p in self._cached_ports:
152 exec('self.%s = bus.port' % p)
153
154 def connectUncachedPorts(self, bus):
155 for p in self._uncached_ports:
156 exec('self.%s = bus.port' % p)
157
158 def connectAllPorts(self, cached_bus, uncached_bus = None):
159 self.connectCachedPorts(cached_bus)
160 if not uncached_bus:
161 uncached_bus = cached_bus
162 self.connectUncachedPorts(uncached_bus)
163
164 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
165 assert(len(self._cached_ports) < 7)
166 self.icache = ic
167 self.dcache = dc
168 self.icache_port = ic.cpu_side
169 self.dcache_port = dc.cpu_side
170 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
|
182
183 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
184 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
185 self.toL2Bus = Bus()
186 self.connectCachedPorts(self.toL2Bus)
187 self.l2cache = l2c
188 self.l2cache.cpu_side = self.toL2Bus.port
189 self._cached_ports = ['l2cache.mem_side']
| 180
181 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
182 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
183 self.toL2Bus = Bus()
184 self.connectCachedPorts(self.toL2Bus)
185 self.l2cache = l2c
186 self.l2cache.cpu_side = self.toL2Bus.port
187 self._cached_ports = ['l2cache.mem_side']
|