1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.SimObject import SimObject
30from m5.params import *
31from m5.proxy import *
32from m5 import build_env
33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
| 1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.SimObject import SimObject
30from m5.params import *
31from m5.proxy import *
32from m5 import build_env
33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
|
40if build_env['FULL_SYSTEM']:
41 if build_env['TARGET_ISA'] == 'alpha':
42 from AlphaTLB import AlphaDTB, AlphaITB
| 40if build_env['TARGET_ISA'] == 'alpha':
41 from AlphaTLB import AlphaDTB, AlphaITB
42elif build_env['TARGET_ISA'] == 'sparc':
43 from SparcTLB import SparcDTB, SparcITB
44elif build_env['TARGET_ISA'] == 'x86':
45 from X86TLB import X86DTB, X86ITB
46elif build_env['TARGET_ISA'] == 'mips':
47 from MipsTLB import MipsDTB, MipsITB
|
43
| 48
|
44 if build_env['TARGET_ISA'] == 'sparc':
45 from SparcTLB import SparcDTB, SparcITB
46
| |
47class BaseCPU(SimObject):
48 type = 'BaseCPU'
49 abstract = True
50
51 system = Param.System(Parent.any, "system object")
52 cpu_id = Param.Int("CPU identifier")
53
54 if build_env['FULL_SYSTEM']:
55 do_quiesce = Param.Bool(True, "enable quiesce instructions")
56 do_checkpoint_insts = Param.Bool(True,
57 "enable checkpoint pseudo instructions")
58 do_statistics_insts = Param.Bool(True,
59 "enable statistics pseudo instructions")
| 49class BaseCPU(SimObject):
50 type = 'BaseCPU'
51 abstract = True
52
53 system = Param.System(Parent.any, "system object")
54 cpu_id = Param.Int("CPU identifier")
55
56 if build_env['FULL_SYSTEM']:
57 do_quiesce = Param.Bool(True, "enable quiesce instructions")
58 do_checkpoint_insts = Param.Bool(True,
59 "enable checkpoint pseudo instructions")
60 do_statistics_insts = Param.Bool(True,
61 "enable statistics pseudo instructions")
|
60
61 if build_env['TARGET_ISA'] == 'sparc':
62 dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
63 itb = Param.SparcITB(SparcITB(), "Instruction TLB")
64 elif build_env['TARGET_ISA'] == 'alpha':
65 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
66 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
67 else:
68 print "Unknown architecture, can't pick TLBs"
69 sys.exit(1)
| |
70 else:
71 workload = VectorParam.Process("processes to run")
72
| 62 else:
63 workload = VectorParam.Process("processes to run")
64
|
| 65 if build_env['TARGET_ISA'] == 'sparc':
66 dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
67 itb = Param.SparcITB(SparcITB(), "Instruction TLB")
68 elif build_env['TARGET_ISA'] == 'alpha':
69 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
70 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
71 elif build_env['TARGET_ISA'] == 'x86':
72 dtb = Param.X86DTB(X86DTB(), "Data TLB")
73 itb = Param.X86ITB(X86ITB(), "Instruction TLB")
74 elif build_env['TARGET_ISA'] == 'mips':
75 dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
76 itb = Param.MipsITB(MipsITB(), "Instruction TLB")
77 else:
78 print "Don't know what TLB to use for ISA %s" % \
79 build_env['TARGET_ISA']
80 sys.exit(1)
81
|
73 max_insts_all_threads = Param.Counter(0,
74 "terminate when all threads have reached this inst count")
75 max_insts_any_thread = Param.Counter(0,
76 "terminate when any thread reaches this inst count")
77 max_loads_all_threads = Param.Counter(0,
78 "terminate when all threads have reached this load count")
79 max_loads_any_thread = Param.Counter(0,
80 "terminate when any thread reaches this load count")
81 progress_interval = Param.Tick(0,
82 "interval to print out the progress message")
83
84 defer_registration = Param.Bool(False,
85 "defer registration with system (for sampling)")
86
87 clock = Param.Clock('1t', "clock speed")
88 phase = Param.Latency('0ns', "clock phase")
89
90 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
91
92 _mem_ports = []
93
94 def connectMemPorts(self, bus):
95 for p in self._mem_ports:
96 if p != 'physmem_port':
97 exec('self.%s = bus.port' % p)
98
99 def addPrivateSplitL1Caches(self, ic, dc):
100 assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
101 self.icache = ic
102 self.dcache = dc
103 self.icache_port = ic.cpu_side
104 self.dcache_port = dc.cpu_side
105 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
106
107 def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
108 self.addPrivateSplitL1Caches(ic, dc)
109 self.toL2Bus = Bus()
110 self.connectMemPorts(self.toL2Bus)
111 self.l2cache = l2c
112 self.l2cache.cpu_side = self.toL2Bus.port
113 self._mem_ports = ['l2cache.mem_side']
| 82 max_insts_all_threads = Param.Counter(0,
83 "terminate when all threads have reached this inst count")
84 max_insts_any_thread = Param.Counter(0,
85 "terminate when any thread reaches this inst count")
86 max_loads_all_threads = Param.Counter(0,
87 "terminate when all threads have reached this load count")
88 max_loads_any_thread = Param.Counter(0,
89 "terminate when any thread reaches this load count")
90 progress_interval = Param.Tick(0,
91 "interval to print out the progress message")
92
93 defer_registration = Param.Bool(False,
94 "defer registration with system (for sampling)")
95
96 clock = Param.Clock('1t', "clock speed")
97 phase = Param.Latency('0ns', "clock phase")
98
99 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
100
101 _mem_ports = []
102
103 def connectMemPorts(self, bus):
104 for p in self._mem_ports:
105 if p != 'physmem_port':
106 exec('self.%s = bus.port' % p)
107
108 def addPrivateSplitL1Caches(self, ic, dc):
109 assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
110 self.icache = ic
111 self.dcache = dc
112 self.icache_port = ic.cpu_side
113 self.dcache_port = dc.cpu_side
114 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
115
116 def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
117 self.addPrivateSplitL1Caches(ic, dc)
118 self.toL2Bus = Bus()
119 self.connectMemPorts(self.toL2Bus)
120 self.l2cache = l2c
121 self.l2cache.cpu_side = self.toL2Bus.port
122 self._mem_ports = ['l2cache.mem_side']
|