1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.SimObject import *
47from m5.defines import buildEnv
48from m5.params import *
49from m5.proxy import *
50
51from XBar import L2XBar
52from InstTracer import InstTracer
53from CPUTracers import ExeTracer
54from MemObject import MemObject
55from ClockDomain import *
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60 from AlphaTLB import AlphaDTB, AlphaITB
61 from AlphaInterrupts import AlphaInterrupts
62 from AlphaISA import AlphaISA
63 isa_class = AlphaISA
64elif buildEnv['TARGET_ISA'] == 'sparc':
65 from SparcTLB import SparcTLB
66 from SparcInterrupts import SparcInterrupts
67 from SparcISA import SparcISA
68 isa_class = SparcISA
69elif buildEnv['TARGET_ISA'] == 'x86':
70 from X86TLB import X86TLB
71 from X86LocalApic import X86LocalApic
72 from X86ISA import X86ISA
73 isa_class = X86ISA
74elif buildEnv['TARGET_ISA'] == 'mips':
75 from MipsTLB import MipsTLB
76 from MipsInterrupts import MipsInterrupts
77 from MipsISA import MipsISA
78 isa_class = MipsISA
79elif buildEnv['TARGET_ISA'] == 'arm':
80 from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
81 from ArmInterrupts import ArmInterrupts
82 from ArmISA import ArmISA
83 isa_class = ArmISA
84elif buildEnv['TARGET_ISA'] == 'power':
85 from PowerTLB import PowerTLB
86 from PowerInterrupts import PowerInterrupts
87 from PowerISA import PowerISA
88 isa_class = PowerISA
89elif buildEnv['TARGET_ISA'] == 'riscv':
90 from RiscvTLB import RiscvTLB
91 from RiscvInterrupts import RiscvInterrupts
92 from RiscvISA import RiscvISA
93 isa_class = RiscvISA
94
95class BaseCPU(MemObject):
96 type = 'BaseCPU'
97 abstract = True
98 cxx_header = "cpu/base.hh"
99
100 cxx_exports = [
101 PyBindMethod("switchOut"),
102 PyBindMethod("takeOverFrom"),
103 PyBindMethod("switchedOut"),
104 PyBindMethod("flushTLBs"),
105 PyBindMethod("totalInsts"),
106 PyBindMethod("scheduleInstStop"),
107 PyBindMethod("scheduleLoadStop"),
108 PyBindMethod("getCurrentInstCount"),
109 ]
110
111 @classmethod
112 def memory_mode(cls):
113 """Which memory mode does this CPU require?"""
114 return 'invalid'
115
116 @classmethod
117 def require_caches(cls):
118 """Does the CPU model require caches?
119
120 Some CPU models might make assumptions that require them to
121 have caches.
122 """
123 return False
124
125 @classmethod
126 def support_take_over(cls):
127 """Does the CPU model support CPU takeOverFrom?"""
128 return False
129
130 def takeOverFrom(self, old_cpu):
131 self._ccObject.takeOverFrom(old_cpu._ccObject)
132
133
134 system = Param.System(Parent.any, "system object")
135 cpu_id = Param.Int(-1, "CPU identifier")
136 socket_id = Param.Unsigned(0, "Physical Socket identifier")
137 numThreads = Param.Unsigned(1, "number of HW thread contexts")
138
139 function_trace = Param.Bool(False, "Enable function trace")
140 function_trace_start = Param.Tick(0, "Tick to start function trace")
141
142 checker = Param.BaseCPU(NULL, "checker CPU")
143
144 syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry")
145
146 do_checkpoint_insts = Param.Bool(True,
147 "enable checkpoint pseudo instructions")
148 do_statistics_insts = Param.Bool(True,
149 "enable statistics pseudo instructions")
150
151 profile = Param.Latency('0ns', "trace the kernel stack")
152 do_quiesce = Param.Bool(True, "enable quiesce instructions")
153
| 1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.SimObject import *
47from m5.defines import buildEnv
48from m5.params import *
49from m5.proxy import *
50
51from XBar import L2XBar
52from InstTracer import InstTracer
53from CPUTracers import ExeTracer
54from MemObject import MemObject
55from ClockDomain import *
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60 from AlphaTLB import AlphaDTB, AlphaITB
61 from AlphaInterrupts import AlphaInterrupts
62 from AlphaISA import AlphaISA
63 isa_class = AlphaISA
64elif buildEnv['TARGET_ISA'] == 'sparc':
65 from SparcTLB import SparcTLB
66 from SparcInterrupts import SparcInterrupts
67 from SparcISA import SparcISA
68 isa_class = SparcISA
69elif buildEnv['TARGET_ISA'] == 'x86':
70 from X86TLB import X86TLB
71 from X86LocalApic import X86LocalApic
72 from X86ISA import X86ISA
73 isa_class = X86ISA
74elif buildEnv['TARGET_ISA'] == 'mips':
75 from MipsTLB import MipsTLB
76 from MipsInterrupts import MipsInterrupts
77 from MipsISA import MipsISA
78 isa_class = MipsISA
79elif buildEnv['TARGET_ISA'] == 'arm':
80 from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
81 from ArmInterrupts import ArmInterrupts
82 from ArmISA import ArmISA
83 isa_class = ArmISA
84elif buildEnv['TARGET_ISA'] == 'power':
85 from PowerTLB import PowerTLB
86 from PowerInterrupts import PowerInterrupts
87 from PowerISA import PowerISA
88 isa_class = PowerISA
89elif buildEnv['TARGET_ISA'] == 'riscv':
90 from RiscvTLB import RiscvTLB
91 from RiscvInterrupts import RiscvInterrupts
92 from RiscvISA import RiscvISA
93 isa_class = RiscvISA
94
95class BaseCPU(MemObject):
96 type = 'BaseCPU'
97 abstract = True
98 cxx_header = "cpu/base.hh"
99
100 cxx_exports = [
101 PyBindMethod("switchOut"),
102 PyBindMethod("takeOverFrom"),
103 PyBindMethod("switchedOut"),
104 PyBindMethod("flushTLBs"),
105 PyBindMethod("totalInsts"),
106 PyBindMethod("scheduleInstStop"),
107 PyBindMethod("scheduleLoadStop"),
108 PyBindMethod("getCurrentInstCount"),
109 ]
110
111 @classmethod
112 def memory_mode(cls):
113 """Which memory mode does this CPU require?"""
114 return 'invalid'
115
116 @classmethod
117 def require_caches(cls):
118 """Does the CPU model require caches?
119
120 Some CPU models might make assumptions that require them to
121 have caches.
122 """
123 return False
124
125 @classmethod
126 def support_take_over(cls):
127 """Does the CPU model support CPU takeOverFrom?"""
128 return False
129
130 def takeOverFrom(self, old_cpu):
131 self._ccObject.takeOverFrom(old_cpu._ccObject)
132
133
134 system = Param.System(Parent.any, "system object")
135 cpu_id = Param.Int(-1, "CPU identifier")
136 socket_id = Param.Unsigned(0, "Physical Socket identifier")
137 numThreads = Param.Unsigned(1, "number of HW thread contexts")
138
139 function_trace = Param.Bool(False, "Enable function trace")
140 function_trace_start = Param.Tick(0, "Tick to start function trace")
141
142 checker = Param.BaseCPU(NULL, "checker CPU")
143
144 syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry")
145
146 do_checkpoint_insts = Param.Bool(True,
147 "enable checkpoint pseudo instructions")
148 do_statistics_insts = Param.Bool(True,
149 "enable statistics pseudo instructions")
150
151 profile = Param.Latency('0ns', "trace the kernel stack")
152 do_quiesce = Param.Bool(True, "enable quiesce instructions")
153
|
154 workload = VectorParam.Process([], "processes to run")
155
156 if buildEnv['TARGET_ISA'] == 'sparc':
157 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
158 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
159 interrupts = VectorParam.SparcInterrupts(
160 [], "Interrupt Controller")
161 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
162 elif buildEnv['TARGET_ISA'] == 'alpha':
163 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
164 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
165 interrupts = VectorParam.AlphaInterrupts(
166 [], "Interrupt Controller")
167 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
168 elif buildEnv['TARGET_ISA'] == 'x86':
169 dtb = Param.X86TLB(X86TLB(), "Data TLB")
170 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
171 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
172 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
173 elif buildEnv['TARGET_ISA'] == 'mips':
174 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
175 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
176 interrupts = VectorParam.MipsInterrupts(
177 [], "Interrupt Controller")
178 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
179 elif buildEnv['TARGET_ISA'] == 'arm':
180 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
181 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
182 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
183 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
184 interrupts = VectorParam.ArmInterrupts(
185 [], "Interrupt Controller")
186 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
187 elif buildEnv['TARGET_ISA'] == 'power':
188 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
189 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
190 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
191 interrupts = VectorParam.PowerInterrupts(
192 [], "Interrupt Controller")
193 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
194 elif buildEnv['TARGET_ISA'] == 'riscv':
195 dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
196 itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
197 interrupts = VectorParam.RiscvInterrupts(
198 [], "Interrupt Controller")
199 isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
200 else:
201 print "Don't know what TLB to use for ISA %s" % \
202 buildEnv['TARGET_ISA']
203 sys.exit(1)
204
205 max_insts_all_threads = Param.Counter(0,
206 "terminate when all threads have reached this inst count")
207 max_insts_any_thread = Param.Counter(0,
208 "terminate when any thread reaches this inst count")
209 simpoint_start_insts = VectorParam.Counter([],
210 "starting instruction counts of simpoints")
211 max_loads_all_threads = Param.Counter(0,
212 "terminate when all threads have reached this load count")
213 max_loads_any_thread = Param.Counter(0,
214 "terminate when any thread reaches this load count")
215 progress_interval = Param.Frequency('0Hz',
216 "frequency to print out the progress message")
217
218 switched_out = Param.Bool(False,
219 "Leave the CPU switched out after startup (used when switching " \
220 "between CPU models)")
221
222 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
223
224 icache_port = MasterPort("Instruction Port")
225 dcache_port = MasterPort("Data Port")
226 _cached_ports = ['icache_port', 'dcache_port']
227
228 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
229 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
230
231 _uncached_slave_ports = []
232 _uncached_master_ports = []
233 if buildEnv['TARGET_ISA'] == 'x86':
234 _uncached_slave_ports += ["interrupts[0].pio",
235 "interrupts[0].int_slave"]
236 _uncached_master_ports += ["interrupts[0].int_master"]
237
238 def createInterruptController(self):
239 if buildEnv['TARGET_ISA'] == 'sparc':
240 self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
241 elif buildEnv['TARGET_ISA'] == 'alpha':
242 self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
243 elif buildEnv['TARGET_ISA'] == 'x86':
244 self.apic_clk_domain = DerivedClockDomain(clk_domain =
245 Parent.clk_domain,
246 clk_divider = 16)
247 self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
248 pio_addr=0x2000000000000000)
249 for i in xrange(self.numThreads)]
250 _localApic = self.interrupts
251 elif buildEnv['TARGET_ISA'] == 'mips':
252 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
253 elif buildEnv['TARGET_ISA'] == 'arm':
254 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
255 elif buildEnv['TARGET_ISA'] == 'power':
256 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
257 elif buildEnv['TARGET_ISA'] == 'riscv':
258 self.interrupts = \
259 [RiscvInterrupts() for i in xrange(self.numThreads)]
260 else:
261 print "Don't know what Interrupt Controller to use for ISA %s" % \
262 buildEnv['TARGET_ISA']
263 sys.exit(1)
264
265 def connectCachedPorts(self, bus):
266 for p in self._cached_ports:
267 exec('self.%s = bus.slave' % p)
268
269 def connectUncachedPorts(self, bus):
270 for p in self._uncached_slave_ports:
271 exec('self.%s = bus.master' % p)
272 for p in self._uncached_master_ports:
273 exec('self.%s = bus.slave' % p)
274
275 def connectAllPorts(self, cached_bus, uncached_bus = None):
276 self.connectCachedPorts(cached_bus)
277 if not uncached_bus:
278 uncached_bus = cached_bus
279 self.connectUncachedPorts(uncached_bus)
280
281 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
282 self.icache = ic
283 self.dcache = dc
284 self.icache_port = ic.cpu_side
285 self.dcache_port = dc.cpu_side
286 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
287 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
288 if iwc and dwc:
289 self.itb_walker_cache = iwc
290 self.dtb_walker_cache = dwc
291 self.itb.walker.port = iwc.cpu_side
292 self.dtb.walker.port = dwc.cpu_side
293 self._cached_ports += ["itb_walker_cache.mem_side", \
294 "dtb_walker_cache.mem_side"]
295 else:
296 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
297
298 # Checker doesn't need its own tlb caches because it does
299 # functional accesses only
300 if self.checker != NULL:
301 self._cached_ports += ["checker.itb.walker.port", \
302 "checker.dtb.walker.port"]
303
304 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
305 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
306 self.toL2Bus = L2XBar()
307 self.connectCachedPorts(self.toL2Bus)
308 self.l2cache = l2c
309 self.toL2Bus.master = self.l2cache.cpu_side
310 self._cached_ports = ['l2cache.mem_side']
311
312 def createThreads(self):
313 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
314 if self.checker != NULL:
315 self.checker.createThreads()
316
317 def addCheckerCpu(self):
318 pass
| 157 workload = VectorParam.Process([], "processes to run")
158
159 if buildEnv['TARGET_ISA'] == 'sparc':
160 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
161 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
162 interrupts = VectorParam.SparcInterrupts(
163 [], "Interrupt Controller")
164 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
165 elif buildEnv['TARGET_ISA'] == 'alpha':
166 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
167 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
168 interrupts = VectorParam.AlphaInterrupts(
169 [], "Interrupt Controller")
170 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
171 elif buildEnv['TARGET_ISA'] == 'x86':
172 dtb = Param.X86TLB(X86TLB(), "Data TLB")
173 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
174 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
175 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
176 elif buildEnv['TARGET_ISA'] == 'mips':
177 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
178 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
179 interrupts = VectorParam.MipsInterrupts(
180 [], "Interrupt Controller")
181 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
182 elif buildEnv['TARGET_ISA'] == 'arm':
183 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
184 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
185 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
186 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
187 interrupts = VectorParam.ArmInterrupts(
188 [], "Interrupt Controller")
189 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
190 elif buildEnv['TARGET_ISA'] == 'power':
191 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
192 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
193 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
194 interrupts = VectorParam.PowerInterrupts(
195 [], "Interrupt Controller")
196 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
197 elif buildEnv['TARGET_ISA'] == 'riscv':
198 dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
199 itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
200 interrupts = VectorParam.RiscvInterrupts(
201 [], "Interrupt Controller")
202 isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
203 else:
204 print "Don't know what TLB to use for ISA %s" % \
205 buildEnv['TARGET_ISA']
206 sys.exit(1)
207
208 max_insts_all_threads = Param.Counter(0,
209 "terminate when all threads have reached this inst count")
210 max_insts_any_thread = Param.Counter(0,
211 "terminate when any thread reaches this inst count")
212 simpoint_start_insts = VectorParam.Counter([],
213 "starting instruction counts of simpoints")
214 max_loads_all_threads = Param.Counter(0,
215 "terminate when all threads have reached this load count")
216 max_loads_any_thread = Param.Counter(0,
217 "terminate when any thread reaches this load count")
218 progress_interval = Param.Frequency('0Hz',
219 "frequency to print out the progress message")
220
221 switched_out = Param.Bool(False,
222 "Leave the CPU switched out after startup (used when switching " \
223 "between CPU models)")
224
225 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
226
227 icache_port = MasterPort("Instruction Port")
228 dcache_port = MasterPort("Data Port")
229 _cached_ports = ['icache_port', 'dcache_port']
230
231 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
232 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
233
234 _uncached_slave_ports = []
235 _uncached_master_ports = []
236 if buildEnv['TARGET_ISA'] == 'x86':
237 _uncached_slave_ports += ["interrupts[0].pio",
238 "interrupts[0].int_slave"]
239 _uncached_master_ports += ["interrupts[0].int_master"]
240
241 def createInterruptController(self):
242 if buildEnv['TARGET_ISA'] == 'sparc':
243 self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
244 elif buildEnv['TARGET_ISA'] == 'alpha':
245 self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
246 elif buildEnv['TARGET_ISA'] == 'x86':
247 self.apic_clk_domain = DerivedClockDomain(clk_domain =
248 Parent.clk_domain,
249 clk_divider = 16)
250 self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
251 pio_addr=0x2000000000000000)
252 for i in xrange(self.numThreads)]
253 _localApic = self.interrupts
254 elif buildEnv['TARGET_ISA'] == 'mips':
255 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
256 elif buildEnv['TARGET_ISA'] == 'arm':
257 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
258 elif buildEnv['TARGET_ISA'] == 'power':
259 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
260 elif buildEnv['TARGET_ISA'] == 'riscv':
261 self.interrupts = \
262 [RiscvInterrupts() for i in xrange(self.numThreads)]
263 else:
264 print "Don't know what Interrupt Controller to use for ISA %s" % \
265 buildEnv['TARGET_ISA']
266 sys.exit(1)
267
268 def connectCachedPorts(self, bus):
269 for p in self._cached_ports:
270 exec('self.%s = bus.slave' % p)
271
272 def connectUncachedPorts(self, bus):
273 for p in self._uncached_slave_ports:
274 exec('self.%s = bus.master' % p)
275 for p in self._uncached_master_ports:
276 exec('self.%s = bus.slave' % p)
277
278 def connectAllPorts(self, cached_bus, uncached_bus = None):
279 self.connectCachedPorts(cached_bus)
280 if not uncached_bus:
281 uncached_bus = cached_bus
282 self.connectUncachedPorts(uncached_bus)
283
284 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
285 self.icache = ic
286 self.dcache = dc
287 self.icache_port = ic.cpu_side
288 self.dcache_port = dc.cpu_side
289 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
290 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
291 if iwc and dwc:
292 self.itb_walker_cache = iwc
293 self.dtb_walker_cache = dwc
294 self.itb.walker.port = iwc.cpu_side
295 self.dtb.walker.port = dwc.cpu_side
296 self._cached_ports += ["itb_walker_cache.mem_side", \
297 "dtb_walker_cache.mem_side"]
298 else:
299 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
300
301 # Checker doesn't need its own tlb caches because it does
302 # functional accesses only
303 if self.checker != NULL:
304 self._cached_ports += ["checker.itb.walker.port", \
305 "checker.dtb.walker.port"]
306
307 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
308 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
309 self.toL2Bus = L2XBar()
310 self.connectCachedPorts(self.toL2Bus)
311 self.l2cache = l2c
312 self.toL2Bus.master = self.l2cache.cpu_side
313 self._cached_ports = ['l2cache.mem_side']
314
315 def createThreads(self):
316 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
317 if self.checker != NULL:
318 self.checker.createThreads()
319
320 def addCheckerCpu(self):
321 pass
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